initial commit
This commit is contained in:
commit
a71c24073e
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Badge/Badge-backups/Badge-2025-02-19_104425.zip
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Badge/Badge-backups/Badge-2025-02-22_115836.zip
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Badge/Badge-backups/Badge-2025-02-22_120909.zip
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Badge/Badge-backups/Badge-2025-02-26_210024.zip
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Badge/Badge-backups/Badge-2025-02-26_213747.zip
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Badge/Badge-backups/Badge-2025-02-28_162223.zip
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Badge/Badge-backups/Badge-2025-03-03_220708.zip
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Badge/Badge-backups/Badge-2025-03-03_221819.zip
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Badge/Badge-backups/Badge-2025-03-13_183336.zip
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Badge/Badge.kicad_pcb
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Badge/Badge.kicad_pcb
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Badge/Badge.kicad_prl
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131
Badge/Badge.kicad_prl
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|||||||
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{
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
"zones": true
|
||||||
|
},
|
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|
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|
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|
"vias",
|
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|
"footprint_text",
|
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|
"footprint_anchors",
|
||||||
|
"ratsnest",
|
||||||
|
"grid",
|
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|
"footprints_front",
|
||||||
|
"footprints_back",
|
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|
"footprint_values",
|
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|
"footprint_references",
|
||||||
|
"tracks",
|
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|
"drc_errors",
|
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|
"drawing_sheet",
|
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|
"bitmaps",
|
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|
"pads",
|
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|
"zones",
|
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|
"drc_warnings",
|
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|
"locked_item_shadows",
|
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|
"conflict_shadows",
|
||||||
|
"shapes"
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
},
|
||||||
|
"meta": {
|
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|
"filename": "Badge.kicad_prl",
|
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|
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|
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|
},
|
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|
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|
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|
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false,
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
},
|
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|
"schematic": {
|
||||||
|
"selection_filter": {
|
||||||
|
"graphics": true,
|
||||||
|
"images": true,
|
||||||
|
"labels": true,
|
||||||
|
"lockedItems": false,
|
||||||
|
"otherItems": true,
|
||||||
|
"pins": true,
|
||||||
|
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|
||||||
|
"text": true,
|
||||||
|
"wires": true
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
615
Badge/Badge.kicad_pro
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Badge/Badge.kicad_pro
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|||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"3dviewports": [],
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"dimension_units": 3,
|
||||||
|
"dimensions": {
|
||||||
|
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|
||||||
|
"extension_offset": 500000,
|
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|
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|
||||||
|
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|
||||||
|
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|
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|
"units_format": 1
|
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|
},
|
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|
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|
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|
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|
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|
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|
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|
"fab_text_size_v": 1.0,
|
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|
"fab_text_thickness": 0.15,
|
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|
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|
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|
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|
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|
||||||
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"other_text_thickness": 0.15,
|
||||||
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|
||||||
|
"pads": {
|
||||||
|
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|
||||||
|
"height": 1.8,
|
||||||
|
"width": 3.4
|
||||||
|
},
|
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|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
}
|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"connection_width": "warning",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"copper_sliver": "warning",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"creepage": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"footprint": "error",
|
||||||
|
"footprint_filters_mismatch": "ignore",
|
||||||
|
"footprint_symbol_mismatch": "warning",
|
||||||
|
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|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"hole_to_hole": "error",
|
||||||
|
"holes_co_located": "warning",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"isolated_copper": "warning",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"lib_footprint_issues": "warning",
|
||||||
|
"lib_footprint_mismatch": "warning",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"mirrored_text_on_front_layer": "warning",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"nonmirrored_text_on_back_layer": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "warning",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_edge_clearance": "warning",
|
||||||
|
"silk_over_copper": "warning",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"solder_mask_bridge": "error",
|
||||||
|
"starved_thermal": "error",
|
||||||
|
"text_height": "warning",
|
||||||
|
"text_thickness": "warning",
|
||||||
|
"through_hole_pad_without_hole": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_angle": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_segment_length": "error",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
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|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"teardrop_options": [
|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
}
|
||||||
|
],
|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"td_target_name": "td_rect_shape",
|
||||||
|
"td_width_to_size_filter_ratio": 0.9
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"td_allow_use_two_tracks": true,
|
||||||
|
"td_curve_segcount": 1,
|
||||||
|
"td_height_ratio": 1.0,
|
||||||
|
"td_length_ratio": 0.5,
|
||||||
|
"td_maxheight": 2.0,
|
||||||
|
"td_maxlen": 1.0,
|
||||||
|
"td_on_pad_in_zone": false,
|
||||||
|
"td_target_name": "td_track_end",
|
||||||
|
"td_width_to_size_filter_ratio": 0.9
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"track_widths": [],
|
||||||
|
"tuning_pattern_settings": {
|
||||||
|
"diff_pair_defaults": {
|
||||||
|
"corner_radius_percentage": 80,
|
||||||
|
"corner_style": 1,
|
||||||
|
"max_amplitude": 1.0,
|
||||||
|
"min_amplitude": 0.2,
|
||||||
|
"single_sided": false,
|
||||||
|
"spacing": 1.0
|
||||||
|
},
|
||||||
|
"diff_pair_skew_defaults": {
|
||||||
|
"corner_radius_percentage": 80,
|
||||||
|
"corner_style": 1,
|
||||||
|
"max_amplitude": 1.0,
|
||||||
|
"min_amplitude": 0.2,
|
||||||
|
"single_sided": false,
|
||||||
|
"spacing": 0.6
|
||||||
|
},
|
||||||
|
"single_track_defaults": {
|
||||||
|
"corner_radius_percentage": 80,
|
||||||
|
"corner_style": 1,
|
||||||
|
"max_amplitude": 1.0,
|
||||||
|
"min_amplitude": 0.2,
|
||||||
|
"single_sided": false,
|
||||||
|
"spacing": 0.6
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"via_dimensions": [],
|
||||||
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||||||
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||||||
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||||||
|
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||||||
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||||||
|
2,
|
||||||
|
2
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||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_entry_needed": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"conflicting_netclasses": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_reference": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"endpoint_off_grid": "warning",
|
||||||
|
"extra_units": "error",
|
||||||
|
"footprint_filter": "ignore",
|
||||||
|
"footprint_link_issues": "warning",
|
||||||
|
"four_way_junction": "ignore",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"label_multiple_wires": "warning",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"lib_symbol_mismatch": "warning",
|
||||||
|
"missing_bidi_pin": "warning",
|
||||||
|
"missing_input_pin": "warning",
|
||||||
|
"missing_power_pin": "error",
|
||||||
|
"missing_unit": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"same_local_global_label": "warning",
|
||||||
|
"similar_label_and_power": "warning",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"similar_power": "warning",
|
||||||
|
"simulation_model_issue": "ignore",
|
||||||
|
"single_global_label": "ignore",
|
||||||
|
"unannotated": "error",
|
||||||
|
"unconnected_wire_endpoint": "warning",
|
||||||
|
"unit_value_mismatch": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
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||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "Badge.kicad_pro",
|
||||||
|
"version": 3
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
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||||||
|
{
|
||||||
|
"bus_width": 12,
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||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"priority": 2147483647,
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.2,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 4
|
||||||
|
},
|
||||||
|
"net_colors": null,
|
||||||
|
"netclass_assignments": null,
|
||||||
|
"netclass_patterns": []
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"plot": "",
|
||||||
|
"pos_files": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
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||||||
|
"svg": "",
|
||||||
|
"vrml": ""
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||||||
|
},
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||||||
|
"page_layout_descr_file": ""
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||||||
|
},
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||||||
|
"schematic": {
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||||||
|
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||||||
|
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||||||
|
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||||||
|
"bom_fmt_settings": {
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||||||
|
"field_delimiter": ",",
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||||||
|
"keep_line_breaks": false,
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||||||
|
"keep_tabs": false,
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||||||
|
"name": "CSV",
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||||||
|
"ref_delimiter": ",",
|
||||||
|
"ref_range_delimiter": "",
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||||||
|
"string_delimiter": "\""
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||||||
|
},
|
||||||
|
"bom_presets": [],
|
||||||
|
"bom_settings": {
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||||||
|
"exclude_dnp": false,
|
||||||
|
"fields_ordered": [
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||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Reference",
|
||||||
|
"name": "Reference",
|
||||||
|
"show": true
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||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Value",
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||||||
|
"name": "Value",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Datasheet",
|
||||||
|
"name": "Datasheet",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Footprint",
|
||||||
|
"name": "Footprint",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Qty",
|
||||||
|
"name": "${QUANTITY}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "DNP",
|
||||||
|
"name": "${DNP}",
|
||||||
|
"show": true
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"filter_string": "",
|
||||||
|
"group_symbols": true,
|
||||||
|
"include_excluded_from_bom": false,
|
||||||
|
"name": "Grouped By Value",
|
||||||
|
"sort_asc": true,
|
||||||
|
"sort_field": "Reference"
|
||||||
|
},
|
||||||
|
"connection_grid_size": 50.0,
|
||||||
|
"drawing": {
|
||||||
|
"dashed_lines_dash_length_ratio": 12.0,
|
||||||
|
"dashed_lines_gap_length_ratio": 3.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"field_names": [],
|
||||||
|
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|
||||||
|
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|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"label_size_ratio": 0.375,
|
||||||
|
"operating_point_overlay_i_precision": 3,
|
||||||
|
"operating_point_overlay_i_range": "~A",
|
||||||
|
"operating_point_overlay_v_precision": 3,
|
||||||
|
"operating_point_overlay_v_range": "~V",
|
||||||
|
"overbar_offset_ratio": 1.23,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.15
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"ngspice": {
|
||||||
|
"fix_include_paths": true,
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"model_mode": 4,
|
||||||
|
"workbook_filename": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"space_save_all_events": true,
|
||||||
|
"spice_current_sheet_as_root": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"spice_model_current_sheet_as_root": true,
|
||||||
|
"spice_save_all_currents": false,
|
||||||
|
"spice_save_all_dissipations": false,
|
||||||
|
"spice_save_all_voltages": false,
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"04bc1928-8036-4a53-8629-9e231f1838ba",
|
||||||
|
"Root"
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
5703
Badge/Badge.kicad_sch
Normal file
5703
Badge/Badge.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
2
Badge/Badge.round-tracks-config
Normal file
2
Badge/Badge.round-tracks-config
Normal file
@ -0,0 +1,2 @@
|
|||||||
|
Default True 2.0 3
|
||||||
|
False True True
|
||||||
105
Badge/Library.pretty/AA3528.kicad_mod
Normal file
105
Badge/Library.pretty/AA3528.kicad_mod
Normal file
@ -0,0 +1,105 @@
|
|||||||
|
(footprint "AA3528"
|
||||||
|
(version 20240108)
|
||||||
|
(generator "pcbnew")
|
||||||
|
(generator_version "8.0")
|
||||||
|
(layer "F.Cu")
|
||||||
|
(property "Reference" "REF**"
|
||||||
|
(at 0 -0.5 0)
|
||||||
|
(unlocked yes)
|
||||||
|
(layer "F.SilkS")
|
||||||
|
(hide yes)
|
||||||
|
(uuid "96011184-e904-48c4-a7ab-104cecb4f243")
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1 1)
|
||||||
|
(thickness 0.1)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Value" "AA3528"
|
||||||
|
(at 0 1 0)
|
||||||
|
(unlocked yes)
|
||||||
|
(layer "F.Fab")
|
||||||
|
(uuid "6440bdff-a9a5-4b79-af09-cba1569f62e9")
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1 1)
|
||||||
|
(thickness 0.15)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Footprint" ""
|
||||||
|
(at 0 0 0)
|
||||||
|
(unlocked yes)
|
||||||
|
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|
(xy -19.955844 7.678496) (xy -20.24055 6.612231) (xy -20.471651 5.525182) (xy -20.652459 4.420905)
|
||||||
|
(xy -20.78629 3.302957) (xy -20.876456 2.174896) (xy -20.939052 -0.09734) (xy -20.866757 -2.367344)
|
||||||
|
(xy -20.686083 -4.606661) (xy -20.42354 -6.786834) (xy -20.42354 -6.786803) (xy -20.218675 -7.969319)
|
||||||
|
(xy -19.92733 -9.204809) (xy -19.559583 -10.475468) (xy -19.125515 -11.763491) (xy -18.635203 -13.051075)
|
||||||
|
(xy -18.098728 -14.320414) (xy -17.526167 -15.553703) (xy -16.927599 -16.733139) (xy -16.313105 -17.840917)
|
||||||
|
(xy -15.692762 -18.859231) (xy -15.07665 -19.770278) (xy -14.474848 -20.556253) (xy -13.897434 -21.19935)
|
||||||
|
(xy -13.354488 -21.681767) (xy -13.09909 -21.857155) (xy -12.856088 -21.985697) (xy -12.626743 -22.065165)
|
||||||
|
(xy -12.412314 -22.093336)
|
||||||
|
)
|
||||||
|
(stroke
|
||||||
|
(width 0.099999)
|
||||||
|
(type solid)
|
||||||
|
(color 255 0 0 1)
|
||||||
|
)
|
||||||
|
(fill none)
|
||||||
|
(layer "Edge.Cuts")
|
||||||
|
(uuid "0e3af4fe-a2a9-4876-9792-b34e2e3830c0")
|
||||||
|
)
|
||||||
|
)
|
||||||
1
Badge/fabrication-toolkit-options.json
Normal file
1
Badge/fabrication-toolkit-options.json
Normal file
@ -0,0 +1 @@
|
|||||||
|
{"EXTRA_LAYERS": "", "ALL_ACTIVE_LAYERS": false, "EXTEND_EDGE_CUT": false, "ALTERNATIVE_EDGE_CUT": false, "AUTO TRANSLATE": true, "AUTO FILL": true, "EXCLUDE DNP": false}
|
||||||
99366
Badge/fp-info-cache
Normal file
99366
Badge/fp-info-cache
Normal file
File diff suppressed because it is too large
Load Diff
4
Badge/fp-lib-table
Normal file
4
Badge/fp-lib-table
Normal file
@ -0,0 +1,4 @@
|
|||||||
|
(fp_lib_table
|
||||||
|
(version 7)
|
||||||
|
(lib (name "Library")(type "KiCad")(uri "${KIPRJMOD}/Library.pretty")(options "")(descr ""))
|
||||||
|
)
|
||||||
3
Badge/out.log
Normal file
3
Badge/out.log
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
Begin Stretch debug
|
||||||
|
Import BS4
|
||||||
|
Success
|
||||||
BIN
Badge/production/Sewi_Badge_v2.zip
Normal file
BIN
Badge/production/Sewi_Badge_v2.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/Badge_2025-02-22_12-03-26.zip
Normal file
BIN
Badge/production/backups/Badge_2025-02-22_12-03-26.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/Sewi_Badge_v2_2025-02-26_21-42-29.zip
Normal file
BIN
Badge/production/backups/Sewi_Badge_v2_2025-02-26_21-42-29.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/Sewi_Badge_v2_2025-03-03_22-07-03.zip
Normal file
BIN
Badge/production/backups/Sewi_Badge_v2_2025-03-03_22-07-03.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/Sewi_Badge_v2_2025-03-03_22-08-04.zip
Normal file
BIN
Badge/production/backups/Sewi_Badge_v2_2025-03-03_22-08-04.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-11_15-06-11.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-11_15-06-11.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-12_12-18-20.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-12_12-18-20.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-12_15-09-10.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-12_15-09-10.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-12_15-21-48.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-12_15-21-48.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-12_15-43-42.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-12_15-43-42.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-14_12-28-49.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-14_12-28-49.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-14_15-11-34.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-14_15-11-34.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-14_15-22-26.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-14_15-22-26.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-14_22-43-20.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-14_22-43-20.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-15_15-00-58.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-15_15-00-58.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-15_15-19-54.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-15_15-19-54.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-15_16-49-38.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-15_16-49-38.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-17_19-07-12.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-17_19-07-12.zip
Normal file
Binary file not shown.
BIN
Badge/production/backups/badge_2025-02-17_19-22-20.zip
Normal file
BIN
Badge/production/backups/badge_2025-02-17_19-22-20.zip
Normal file
Binary file not shown.
11
Badge/production/bom.csv
Normal file
11
Badge/production/bom.csv
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
Designator,Footprint,Quantity,Value,LCSC Part #
|
||||||
|
BT1,BatteryHolder_Keystone_3034_1x20mm,1,Battery_Cell,
|
||||||
|
C1,0402,1,1uF,
|
||||||
|
"D1, D10, D11, D12, D2, D3, D4, D5, D6, D7, D8, D9",0603,12,LED,
|
||||||
|
J1,JST_SH_SM03B-SRSS-TB_1x03-1MP_P1.00mm_Horizontal,1,Conn_01x03_MountingPin,
|
||||||
|
R1,0402,1,1k,
|
||||||
|
RN1,R_Array_Concave_4x0603,1,56R,
|
||||||
|
SW1,SW_SPST_B3U-3000P,1,SW_Push,
|
||||||
|
"TP1, TP2",TestPoint_Keystone_5015_Micro-Minature,2,TestPoint,
|
||||||
|
TP3,TestPoint_Pad_D2.0mm,1,TestPoint,
|
||||||
|
U1,SOIC-14_3.9x8.7mm_P1.27mm,1,ATSAMD09C13A-SS,
|
||||||
|
24
Badge/production/designators.csv
Normal file
24
Badge/production/designators.csv
Normal file
@ -0,0 +1,24 @@
|
|||||||
|
BT1:1
|
||||||
|
C1:1
|
||||||
|
D1:1
|
||||||
|
D10:1
|
||||||
|
D11:1
|
||||||
|
D12:1
|
||||||
|
D2:1
|
||||||
|
D3:1
|
||||||
|
D4:1
|
||||||
|
D5:1
|
||||||
|
D6:1
|
||||||
|
D7:1
|
||||||
|
D8:1
|
||||||
|
D9:1
|
||||||
|
G***:4
|
||||||
|
J1:1
|
||||||
|
R1:1
|
||||||
|
REF**:1
|
||||||
|
RN1:1
|
||||||
|
SW1:1
|
||||||
|
TP1:1
|
||||||
|
TP2:1
|
||||||
|
TP3:1
|
||||||
|
U1:1
|
||||||
|
73
Badge/production/netlist.ipc
Normal file
73
Badge/production/netlist.ipc
Normal file
@ -0,0 +1,73 @@
|
|||||||
|
P CODE 00
|
||||||
|
P UNITS CUST 0
|
||||||
|
P arrayDim N
|
||||||
|
317GND VIA MD0118PA00X+035666Y-024204X0236Y0000R000S3
|
||||||
|
317GND VIA MD0118PA00X+029766Y-022304X0236Y0000R000S3
|
||||||
|
317NET-(D1-A) VIA MD0118PA00X+042228Y-026289X0236Y0000R000S3
|
||||||
|
317NET-(D1-K) VIA MD0118PA00X+038157Y-021348X0236Y0000R000S3
|
||||||
|
317NET-(D10-A) VIA MD0118PA00X+039955Y-021541X0236Y0000R000S3
|
||||||
|
317NET-(D12-K) VIA MD0118PA00X+035666Y-021604X0236Y0000R000S3
|
||||||
|
327NET-(D1-K) D8 -1 A01X+031455Y-031616X0413Y0374R300S2
|
||||||
|
327NET-(D12-K) D8 -2 A01X+031800Y-031019X0413Y0374R300S2
|
||||||
|
327NET-(D1-A) D10 -1 A01X+041384Y-029167X0413Y0374R030S2
|
||||||
|
327NET-(D10-A) D10 -2 A01X+041981Y-029511X0413Y0374R030S2
|
||||||
|
327NET-(D10-A) D6 -1 A01X+042681Y-023067X0413Y0374R150S2
|
||||||
|
327NET-(D1-K) D6 -2 A01X+042084Y-023411X0413Y0374R150S2
|
||||||
|
327NET-(D1-A) D7 -1 A01X+028784Y-023367X0413Y0374R030S2
|
||||||
|
327NET-(D12-K) D7 -2 A01X+029381Y-023711X0413Y0374R030S2
|
||||||
|
327NET-(D1-K) D11 -1 A01X+039610Y-022137X0413Y0374R300S2
|
||||||
|
327NET-(D10-A) D11 -2 A01X+039955Y-021541X0413Y0374R300S2
|
||||||
|
327NET-(D10-A) D9 -1 A01X+031110Y-021641X0413Y0374R060S2
|
||||||
|
327NET-(D12-K) D9 -2 A01X+031455Y-022237X0413Y0374R060S2
|
||||||
|
327NET-(D12-K) D12 -1 A01X+035666Y-021604X0413Y0374R270S2
|
||||||
|
327NET-(D10-A) D12 -2 A01X+035666Y-020915X0413Y0374R270S2
|
||||||
|
327NET-(D12-K) D2 -1 A01X+029132Y-026535X0413Y0374R180S2
|
||||||
|
327NET-(D1-A) D2 -2 A01X+028443Y-026535X0413Y0374R180S2
|
||||||
|
327NET-(D12-K) D5 -1 A01X+029981Y-029267X0413Y0374R150S2
|
||||||
|
327NET-(D1-K) D5 -2 A01X+029384Y-029611X0413Y0374R150S2
|
||||||
|
327NET-(D1-A) D4 -1 A01X+039310Y-030941X0413Y0374R060S2
|
||||||
|
327NET-(D1-K) D4 -2 A01X+039655Y-031537X0413Y0374R060S2
|
||||||
|
327NET-(D10-A) D3 -1 A01X+042917Y-026289X0413Y0374R180S2
|
||||||
|
327NET-(D1-A) D3 -2 A01X+042228Y-026289X0413Y0374R180S2
|
||||||
|
327NET-(D1-K) D1 -1 A01X+035666Y-032448X0413Y0374R270S2
|
||||||
|
327NET-(D1-A) D1 -2 A01X+035666Y-031759X0413Y0374R270S2
|
||||||
|
327NET-(U1-PA04) TP2 -1 A02X+037266Y-022704X1339Y0709R270S1
|
||||||
|
327NET-(U1-PA04) R1 -1 A02X+037800Y-024238X0281Y0252R045S1
|
||||||
|
327+3V0 R1 -2 A02X+038133Y-024570X0281Y0252R045S1
|
||||||
|
327+3V0 C1 -1 A02X+038540Y-024990X0289Y0244R045S1
|
||||||
|
327GND C1 -2 A02X+038856Y-025306X0289Y0244R045S1
|
||||||
|
327+3V0 BT1 -1 A02X+040007Y-028846X0500Y2000R180S1
|
||||||
|
327+3V0 BT1 -1 A02X+031358Y-028846X0500Y2000R180S1
|
||||||
|
327GND BT1 -2 A02X+035682Y-028846X7008Y0000R180S1
|
||||||
|
327{SLASH}~{RST}) TP3 -1 A02X+043166Y-024504X0787Y0000R180S1
|
||||||
|
327/BUTTON SW1 -1 A02X+042972Y-023155X0354Y0669R255S1
|
||||||
|
327GND SW1 -2 A02X+042626Y-021862X0354Y0669R255S1
|
||||||
|
327/S4 U1 -1 A02X+039811Y-022268X0768Y0236R135S1
|
||||||
|
327/S2 U1 -2 A02X+040165Y-022621X0768Y0236R135S1
|
||||||
|
327/S3 U1 -3 A02X+040518Y-022975X0768Y0236R135S1
|
||||||
|
327/S1 U1 -4 A02X+040872Y-023328X0768Y0236R135S1
|
||||||
|
327/BUTTON U1 -5 A02X+041225Y-023682X0768Y0236R135S1
|
||||||
|
327{SLASH}~{RST}) U1 -6 A02X+041579Y-024036X0768Y0236R135S1
|
||||||
|
327NET-(J1-PIN_1) U1 -7 A02X+041932Y-024389X0768Y0236R135S1
|
||||||
|
327NET-(J1-PIN_3) U1 -8 A02X+040554Y-025767X0768Y0236R135S1
|
||||||
|
327(U1-PA24-PAD9) U1 -9 A02X+040201Y-025414X0768Y0236R135S1
|
||||||
|
327U1-PA25-PAD10) U1 -10 A02X+039847Y-025060X0768Y0236R135S1
|
||||||
|
327GND U1 -11 A02X+039494Y-024706X0768Y0236R135S1
|
||||||
|
327+3V0 U1 -12 A02X+039140Y-024353X0768Y0236R135S1
|
||||||
|
327U1-PA02-PAD13) U1 -13 A02X+038787Y-023999X0768Y0236R135S1
|
||||||
|
327NET-(U1-PA04) U1 -14 A02X+038433Y-023646X0768Y0236R135S1
|
||||||
|
327NET-(J1-PIN_1) J1 -1 A02X+041541Y-026664X0236Y0610R104S1
|
||||||
|
327GND J1 -2 A02X+041446Y-027046X0236Y0610R104S1
|
||||||
|
327NET-(J1-PIN_3) J1 -3 A02X+041351Y-027428X0236Y0610R104S1
|
||||||
|
327GND J1 -MP A02X+043145Y-026536X0472Y0709R104S1
|
||||||
|
327GND J1 -MP A02X+042707Y-028293X0472Y0709R104S1
|
||||||
|
327GND TP1 -1 A02X+034066Y-022704X1339Y0709R090S1
|
||||||
|
327NET-(D1-A) RN1 -1 A02X+038264Y-022017X0354Y0157R045S1
|
||||||
|
327NET-(D12-K) RN1 -2 A02X+038486Y-021794X0354Y0157R045S1
|
||||||
|
327NET-(D1-K) RN1 -3 A02X+038709Y-021572X0354Y0157R045S1
|
||||||
|
327NET-(D10-A) RN1 -4 A02X+038932Y-021349X0354Y0157R045S1
|
||||||
|
327/S4 RN1 -5 A02X+039405Y-021822X0354Y0157R045S1
|
||||||
|
327/S2 RN1 -6 A02X+039182Y-022045X0354Y0157R045S1
|
||||||
|
327/S3 RN1 -7 A02X+038960Y-022267X0354Y0157R045S1
|
||||||
|
327/S1 RN1 -8 A02X+038737Y-022490X0354Y0157R045S1
|
||||||
|
999
|
||||||
22
Badge/production/positions.csv
Normal file
22
Badge/production/positions.csv
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
Designator,Mid X,Mid Y,Rotation,Layer
|
||||||
|
BT1,90.633406,-73.268298,0.0,bottom
|
||||||
|
C1,98.294106,-63.876498,225.0,bottom
|
||||||
|
D1,90.5925,-81.544,90.0,top
|
||||||
|
D10,105.873406,-74.521298,330.0,top
|
||||||
|
D11,101.047406,-55.471298,60.0,top
|
||||||
|
D12,90.5925,-53.999,90.0,top
|
||||||
|
D2,73.119626,-67.399223,180.0,top
|
||||||
|
D3,108.133406,-66.774298,180.0,top
|
||||||
|
D4,100.285406,-79.347298,300.0,top
|
||||||
|
D5,75.393406,-74.775298,210.0,top
|
||||||
|
D6,107.651406,-59.027298,210.0,top
|
||||||
|
D7,73.869406,-59.789298,330.0,top
|
||||||
|
D8,80.333406,-79.546637,60.0,top
|
||||||
|
D9,79.457406,-55.725298,300.0,top
|
||||||
|
J1,107.213106,-69.179698,284.0,bottom
|
||||||
|
R1,96.4345,-61.986,225.0,bottom
|
||||||
|
RN1,98.639523,-55.675521,315.0,bottom
|
||||||
|
SW1,108.709465,-57.171817,165.0,bottom
|
||||||
|
TP1,86.5285,-57.668,270.0,bottom
|
||||||
|
TP2,94.6565,-57.668,90.0,bottom
|
||||||
|
U1,102.064206,-61.004298,225.0,bottom
|
||||||
|
12
Firmware/.buildconfig
Normal file
12
Firmware/.buildconfig
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
[default]
|
||||||
|
name=Default
|
||||||
|
runtime=podman:340af3d12b0a26614807836780c2a5760e6ea9fcb912c2f800f618bd17c0464d
|
||||||
|
toolchain=default
|
||||||
|
config-opts=
|
||||||
|
run-opts=
|
||||||
|
prefix=/var/home/valentinw/Projects/.gnome-builder/projects/Firmware/install/podman-340af3d12b0a26614807836780c2a5760e6ea9fcb912c2f800f618bd17c0464d
|
||||||
|
app-id=
|
||||||
|
postbuild=
|
||||||
|
prebuild=
|
||||||
|
run-command=
|
||||||
|
default=true
|
||||||
6
Firmware/AtmelStart.env_conf
Normal file
6
Firmware/AtmelStart.env_conf
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
<environment>
|
||||||
|
<configurations/>
|
||||||
|
<device-packs>
|
||||||
|
<device-pack device="ATSAMD09C13A" name="SAMD09_DFP" vendor="Atmel" version="1.1.76"/>
|
||||||
|
</device-packs>
|
||||||
|
</environment>
|
||||||
180
Firmware/AtmelStart.gpdsc
Normal file
180
Firmware/AtmelStart.gpdsc
Normal file
@ -0,0 +1,180 @@
|
|||||||
|
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
|
||||||
|
<vendor>Atmel</vendor>
|
||||||
|
<name>My Project</name>
|
||||||
|
<description>Project generated by Atmel Start</description>
|
||||||
|
<url>http://start.atmel.com/</url>
|
||||||
|
<releases>
|
||||||
|
<release version="1.0.1">Initial version</release>
|
||||||
|
</releases>
|
||||||
|
<taxonomy>
|
||||||
|
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
|
||||||
|
</taxonomy>
|
||||||
|
<generators>
|
||||||
|
<generator id="AtmelStart">
|
||||||
|
<description>Atmel Start</description>
|
||||||
|
<select Dname="ATSAMD09C13A" Dvendor="Atmel:3"/>
|
||||||
|
<command>http://start.atmel.com/</command>
|
||||||
|
<files>
|
||||||
|
<file category="generator" name="atmel_start_config.atstart"/>
|
||||||
|
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
|
||||||
|
</files>
|
||||||
|
</generator>
|
||||||
|
</generators>
|
||||||
|
<conditions>
|
||||||
|
<condition id="CMSIS Device Startup">
|
||||||
|
<description>Dependency on CMSIS core and Device Startup components</description>
|
||||||
|
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
|
||||||
|
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
|
||||||
|
</condition>
|
||||||
|
<condition id="ARMCC, GCC, IAR">
|
||||||
|
<require Dname="ATSAMD09C13A"/>
|
||||||
|
<accept Tcompiler="ARMCC"/>
|
||||||
|
<accept Tcompiler="GCC"/>
|
||||||
|
<accept Tcompiler="IAR"/>
|
||||||
|
</condition>
|
||||||
|
<condition id="GCC">
|
||||||
|
<require Dname="ATSAMD09C13A"/>
|
||||||
|
<accept Tcompiler="GCC"/>
|
||||||
|
</condition>
|
||||||
|
</conditions>
|
||||||
|
<components generator="AtmelStart">
|
||||||
|
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
|
||||||
|
<description>Atmel Start Framework</description>
|
||||||
|
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
|
||||||
|
<files>
|
||||||
|
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
|
||||||
|
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
|
||||||
|
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/timer.rst"/>
|
||||||
|
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/wdt.rst"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_wdt.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_time_measure.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_wdt.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_wdt.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_decrement_macro.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_recursion_macro.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
|
||||||
|
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mtb_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvic_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sysctrl_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_systemcontrol_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_systick_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_d09.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_d09.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_timer.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_calendar.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_timer.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m0plus_base.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc_base.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sysctrl/hpl_sysctrl.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/systick/hpl_systick.c"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/wdt/hpl_wdt.c"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/wdt/hpl_wdt_base.h"/>
|
||||||
|
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
|
||||||
|
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_pm_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_rtc_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sysctrl_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_systick_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_wdt_config.h"/>
|
||||||
|
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/rtc"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sysctrl"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/systick"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/wdt"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
|
||||||
|
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||||
|
</files>
|
||||||
|
</component>
|
||||||
|
</components>
|
||||||
|
</package>
|
||||||
865
Firmware/CMSIS/Core/Include/cmsis_armcc.h
Normal file
865
Firmware/CMSIS/Core/Include/cmsis_armcc.h
Normal file
@ -0,0 +1,865 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_armcc.h
|
||||||
|
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ARMCC_H
|
||||||
|
#define __CMSIS_ARMCC_H
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||||
|
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler control architecture macros */
|
||||||
|
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||||
|
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||||
|
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||||
|
|
||||||
|
|
||||||
|
/* CMSIS compiler specific defines */
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE static __forceinline
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __declspec(noreturn)
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ########################### Core Function Access ########################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable IRQ Interrupts
|
||||||
|
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __enable_irq(); */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable IRQ Interrupts
|
||||||
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Control Register
|
||||||
|
\details Returns the content of the Control Register.
|
||||||
|
\return Control Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
return(__regControl);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Control Register
|
||||||
|
\details Writes the given value to the Control Register.
|
||||||
|
\param [in] control Control Register value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
__regControl = control;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get IPSR Register
|
||||||
|
\details Returns the content of the IPSR Register.
|
||||||
|
\return IPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regIPSR __ASM("ipsr");
|
||||||
|
return(__regIPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get APSR Register
|
||||||
|
\details Returns the content of the APSR Register.
|
||||||
|
\return APSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regAPSR __ASM("apsr");
|
||||||
|
return(__regAPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get xPSR Register
|
||||||
|
\details Returns the content of the xPSR Register.
|
||||||
|
\return xPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regXPSR __ASM("xpsr");
|
||||||
|
return(__regXPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Process Stack Pointer
|
||||||
|
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||||
|
\return PSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
return(__regProcessStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Process Stack Pointer
|
||||||
|
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||||
|
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
__regProcessStackPointer = topOfProcStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Main Stack Pointer
|
||||||
|
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||||
|
\return MSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
return(__regMainStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Main Stack Pointer
|
||||||
|
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||||
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
__regMainStackPointer = topOfMainStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Priority Mask
|
||||||
|
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||||
|
\return Priority Mask value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
return(__regPriMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Priority Mask
|
||||||
|
\details Assigns the given value to the Priority Mask Register.
|
||||||
|
\param [in] priMask Priority Mask
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
__regPriMask = (priMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable FIQ
|
||||||
|
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable FIQ
|
||||||
|
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Base Priority
|
||||||
|
\details Returns the current value of the Base Priority register.
|
||||||
|
\return Base Priority register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
return(__regBasePri);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Base Priority
|
||||||
|
\details Assigns the given value to the Base Priority register.
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
__regBasePri = (basePri & 0xFFU);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Base Priority with condition
|
||||||
|
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||||
|
or the new value increases the BASEPRI priority level.
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||||
|
__regBasePriMax = (basePri & 0xFFU);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Fault Mask
|
||||||
|
\details Returns the current value of the Fault Mask register.
|
||||||
|
\return Fault Mask register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
return(__regFaultMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Fault Mask
|
||||||
|
\details Assigns the given value to the Fault Mask register.
|
||||||
|
\param [in] faultMask Fault Mask value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get FPSCR
|
||||||
|
\details Returns the current value of the Floating Point Status/Control register.
|
||||||
|
\return Floating Point Status/Control register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
return(__regfpscr);
|
||||||
|
#else
|
||||||
|
return(0U);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set FPSCR
|
||||||
|
\details Assigns the given value to the Floating Point Status/Control register.
|
||||||
|
\param [in] fpscr Floating Point Status/Control value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
__regfpscr = (fpscr);
|
||||||
|
#else
|
||||||
|
(void)fpscr;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## Core Instruction Access ######################### */
|
||||||
|
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||||
|
Access to dedicated instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief No Operation
|
||||||
|
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
*/
|
||||||
|
#define __NOP __nop
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Wait For Interrupt
|
||||||
|
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFI __wfi
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Wait For Event
|
||||||
|
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFE __wfe
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Send Event
|
||||||
|
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||||
|
*/
|
||||||
|
#define __SEV __sev
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Instruction Synchronization Barrier
|
||||||
|
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
so that all instructions following the ISB are fetched from cache or memory,
|
||||||
|
after the instruction has been completed.
|
||||||
|
*/
|
||||||
|
#define __ISB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__isb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Data Synchronization Barrier
|
||||||
|
\details Acts as a special kind of Data Memory Barrier.
|
||||||
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
|
*/
|
||||||
|
#define __DSB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__dsb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Data Memory Barrier
|
||||||
|
\details Ensures the apparent order of the explicit memory operations before
|
||||||
|
and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
#define __DMB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__dmb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (32 bit)
|
||||||
|
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#define __REV __rev
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (16 bit)
|
||||||
|
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||||
|
{
|
||||||
|
rev16 r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (16 bit)
|
||||||
|
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||||
|
{
|
||||||
|
revsh r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Rotate Right in unsigned value (32 bit)
|
||||||
|
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
|
\param [in] op1 Value to rotate
|
||||||
|
\param [in] op2 Number of Bits to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#define __ROR __ror
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Breakpoint
|
||||||
|
\details Causes the processor to enter Debug state.
|
||||||
|
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||||
|
\param [in] value is ignored by the processor.
|
||||||
|
If required, a debugger can use it to store additional information about the breakpoint.
|
||||||
|
*/
|
||||||
|
#define __BKPT(value) __breakpoint(value)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse bit order of value
|
||||||
|
\details Reverses the bit order of the given value.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
#define __RBIT __rbit
|
||||||
|
#else
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||||
|
|
||||||
|
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||||
|
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||||
|
{
|
||||||
|
result <<= 1U;
|
||||||
|
result |= value & 1U;
|
||||||
|
s--;
|
||||||
|
}
|
||||||
|
result <<= s; /* shift when v's highest bits are zero */
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Count leading zeros
|
||||||
|
\details Counts the number of leading zeros of a data value.
|
||||||
|
\param [in] value Value to count the leading zeros
|
||||||
|
\return number of leading zeros in value
|
||||||
|
*/
|
||||||
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (8 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (16 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (32 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (8 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 8 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (16 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 16 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (32 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 32 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Remove the exclusive lock
|
||||||
|
\details Removes the exclusive lock which is created by LDREX.
|
||||||
|
*/
|
||||||
|
#define __CLREX __clrex
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __SSAT __ssat
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __USAT __usat
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Rotate Right with Extend (32 bit)
|
||||||
|
\details Moves each bit of a bitstring right by one bit.
|
||||||
|
The carry input is shifted in at the left end of the bitstring.
|
||||||
|
\param [in] value Value to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
rrx r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (8 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (16 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (32 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (8 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (16 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (32 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
|
||||||
|
/* ################### Compiler specific Intrinsics ########################### */
|
||||||
|
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||||
|
Access to dedicated SIMD instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
#define __SADD8 __sadd8
|
||||||
|
#define __QADD8 __qadd8
|
||||||
|
#define __SHADD8 __shadd8
|
||||||
|
#define __UADD8 __uadd8
|
||||||
|
#define __UQADD8 __uqadd8
|
||||||
|
#define __UHADD8 __uhadd8
|
||||||
|
#define __SSUB8 __ssub8
|
||||||
|
#define __QSUB8 __qsub8
|
||||||
|
#define __SHSUB8 __shsub8
|
||||||
|
#define __USUB8 __usub8
|
||||||
|
#define __UQSUB8 __uqsub8
|
||||||
|
#define __UHSUB8 __uhsub8
|
||||||
|
#define __SADD16 __sadd16
|
||||||
|
#define __QADD16 __qadd16
|
||||||
|
#define __SHADD16 __shadd16
|
||||||
|
#define __UADD16 __uadd16
|
||||||
|
#define __UQADD16 __uqadd16
|
||||||
|
#define __UHADD16 __uhadd16
|
||||||
|
#define __SSUB16 __ssub16
|
||||||
|
#define __QSUB16 __qsub16
|
||||||
|
#define __SHSUB16 __shsub16
|
||||||
|
#define __USUB16 __usub16
|
||||||
|
#define __UQSUB16 __uqsub16
|
||||||
|
#define __UHSUB16 __uhsub16
|
||||||
|
#define __SASX __sasx
|
||||||
|
#define __QASX __qasx
|
||||||
|
#define __SHASX __shasx
|
||||||
|
#define __UASX __uasx
|
||||||
|
#define __UQASX __uqasx
|
||||||
|
#define __UHASX __uhasx
|
||||||
|
#define __SSAX __ssax
|
||||||
|
#define __QSAX __qsax
|
||||||
|
#define __SHSAX __shsax
|
||||||
|
#define __USAX __usax
|
||||||
|
#define __UQSAX __uqsax
|
||||||
|
#define __UHSAX __uhsax
|
||||||
|
#define __USAD8 __usad8
|
||||||
|
#define __USADA8 __usada8
|
||||||
|
#define __SSAT16 __ssat16
|
||||||
|
#define __USAT16 __usat16
|
||||||
|
#define __UXTB16 __uxtb16
|
||||||
|
#define __UXTAB16 __uxtab16
|
||||||
|
#define __SXTB16 __sxtb16
|
||||||
|
#define __SXTAB16 __sxtab16
|
||||||
|
#define __SMUAD __smuad
|
||||||
|
#define __SMUADX __smuadx
|
||||||
|
#define __SMLAD __smlad
|
||||||
|
#define __SMLADX __smladx
|
||||||
|
#define __SMLALD __smlald
|
||||||
|
#define __SMLALDX __smlaldx
|
||||||
|
#define __SMUSD __smusd
|
||||||
|
#define __SMUSDX __smusdx
|
||||||
|
#define __SMLSD __smlsd
|
||||||
|
#define __SMLSDX __smlsdx
|
||||||
|
#define __SMLSLD __smlsld
|
||||||
|
#define __SMLSLDX __smlsldx
|
||||||
|
#define __SEL __sel
|
||||||
|
#define __QADD __qadd
|
||||||
|
#define __QSUB __qsub
|
||||||
|
|
||||||
|
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||||
|
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||||
|
|
||||||
|
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||||
|
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||||
|
|
||||||
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ARMCC_H */
|
||||||
1869
Firmware/CMSIS/Core/Include/cmsis_armclang.h
Normal file
1869
Firmware/CMSIS/Core/Include/cmsis_armclang.h
Normal file
File diff suppressed because it is too large
Load Diff
266
Firmware/CMSIS/Core/Include/cmsis_compiler.h
Normal file
266
Firmware/CMSIS/Core/Include/cmsis_compiler.h
Normal file
@ -0,0 +1,266 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_compiler.h
|
||||||
|
* @brief CMSIS compiler generic header file
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_COMPILER_H
|
||||||
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 4/5
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 6 (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GNU Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IAR Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI Arm Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TASKING Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __align(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COSMIC Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM _asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
// NO RETURN is automatically detected hence no warning here
|
||||||
|
#define __NO_RETURN
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
|
#define __USED
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __weak
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED @packed
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT @packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION @packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Unknown compiler.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
||||||
2085
Firmware/CMSIS/Core/Include/cmsis_gcc.h
Normal file
2085
Firmware/CMSIS/Core/Include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
935
Firmware/CMSIS/Core/Include/cmsis_iccarm.h
Normal file
935
Firmware/CMSIS/Core/Include/cmsis_iccarm.h
Normal file
@ -0,0 +1,935 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_iccarm.h
|
||||||
|
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||||
|
* @version V5.0.7
|
||||||
|
* @date 19. June 2018
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Copyright (c) 2017-2018 IAR Systems
|
||||||
|
//
|
||||||
|
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||||
|
// you may not use this file except in compliance with the License.
|
||||||
|
// You may obtain a copy of the License at
|
||||||
|
// http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
//
|
||||||
|
// Unless required by applicable law or agreed to in writing, software
|
||||||
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
// See the License for the specific language governing permissions and
|
||||||
|
// limitations under the License.
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ICCARM_H__
|
||||||
|
#define __CMSIS_ICCARM_H__
|
||||||
|
|
||||||
|
#ifndef __ICCARM__
|
||||||
|
#error This file should only be compiled by ICCARM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma system_include
|
||||||
|
|
||||||
|
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||||
|
|
||||||
|
#if (__VER__ >= 8000000)
|
||||||
|
#define __ICCARM_V8 1
|
||||||
|
#else
|
||||||
|
#define __ICCARM_V8 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#elif (__VER__ >= 7080000)
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#else
|
||||||
|
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||||
|
*/
|
||||||
|
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||||
|
/* Macros already defined */
|
||||||
|
#else
|
||||||
|
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||||
|
#if __ARM_ARCH == 6
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif __ARM_ARCH == 7
|
||||||
|
#if __ARM_FEATURE_DSP
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#else
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
#endif /* __ARM_ARCH */
|
||||||
|
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Alternativ core deduction for older ICCARM's */
|
||||||
|
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||||
|
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||||
|
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#else
|
||||||
|
#error "Unknown target."
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#else
|
||||||
|
#define __IAR_M0_FAMILY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __NO_RETURN __attribute__((__noreturn__))
|
||||||
|
#else
|
||||||
|
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED __packed
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __FORCEINLINE
|
||||||
|
#define __FORCEINLINE _Pragma("inline=forced")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint16_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint16_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint32_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint32_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__packed struct __iar_u32 { uint32_t v; };
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __USED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#else
|
||||||
|
#define __USED _Pragma("__root")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __WEAK
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#else
|
||||||
|
#define __WEAK _Pragma("__weak")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||||
|
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||||
|
|
||||||
|
#if defined(__CLZ)
|
||||||
|
#undef __CLZ
|
||||||
|
#endif
|
||||||
|
#if defined(__REVSH)
|
||||||
|
#undef __REVSH
|
||||||
|
#endif
|
||||||
|
#if defined(__RBIT)
|
||||||
|
#undef __RBIT
|
||||||
|
#endif
|
||||||
|
#if defined(__SSAT)
|
||||||
|
#undef __SSAT
|
||||||
|
#endif
|
||||||
|
#if defined(__USAT)
|
||||||
|
#undef __USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "iccarm_builtin.h"
|
||||||
|
|
||||||
|
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||||
|
#define __disable_irq __iar_builtin_disable_interrupt
|
||||||
|
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||||
|
#define __enable_irq __iar_builtin_enable_interrupt
|
||||||
|
#define __arm_rsr __iar_builtin_rsr
|
||||||
|
#define __arm_wsr __iar_builtin_wsr
|
||||||
|
|
||||||
|
|
||||||
|
#define __get_APSR() (__arm_rsr("APSR"))
|
||||||
|
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||||
|
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||||
|
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||||
|
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||||
|
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||||
|
#else
|
||||||
|
#define __get_FPSCR() ( 0 )
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||||
|
#define __get_MSP() (__arm_rsr("MSP"))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __get_MSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||||
|
#endif
|
||||||
|
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||||
|
#define __get_PSP() (__arm_rsr("PSP"))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __get_PSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||||
|
|
||||||
|
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||||
|
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||||
|
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||||
|
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||||
|
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||||
|
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||||
|
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||||
|
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||||
|
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||||
|
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||||
|
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||||
|
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||||
|
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||||
|
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||||
|
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __TZ_get_PSPLIM_NS() (0U)
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||||
|
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||||
|
|
||||||
|
#define __NOP __iar_builtin_no_operation
|
||||||
|
|
||||||
|
#define __CLZ __iar_builtin_CLZ
|
||||||
|
#define __CLREX __iar_builtin_CLREX
|
||||||
|
|
||||||
|
#define __DMB __iar_builtin_DMB
|
||||||
|
#define __DSB __iar_builtin_DSB
|
||||||
|
#define __ISB __iar_builtin_ISB
|
||||||
|
|
||||||
|
#define __LDREXB __iar_builtin_LDREXB
|
||||||
|
#define __LDREXH __iar_builtin_LDREXH
|
||||||
|
#define __LDREXW __iar_builtin_LDREX
|
||||||
|
|
||||||
|
#define __RBIT __iar_builtin_RBIT
|
||||||
|
#define __REV __iar_builtin_REV
|
||||||
|
#define __REV16 __iar_builtin_REV16
|
||||||
|
|
||||||
|
__IAR_FT int16_t __REVSH(int16_t val)
|
||||||
|
{
|
||||||
|
return (int16_t) __iar_builtin_REVSH(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __ROR __iar_builtin_ROR
|
||||||
|
#define __RRX __iar_builtin_RRX
|
||||||
|
|
||||||
|
#define __SEV __iar_builtin_SEV
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __SSAT __iar_builtin_SSAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __STREXB __iar_builtin_STREXB
|
||||||
|
#define __STREXH __iar_builtin_STREXH
|
||||||
|
#define __STREXW __iar_builtin_STREX
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __USAT __iar_builtin_USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __WFE __iar_builtin_WFE
|
||||||
|
#define __WFI __iar_builtin_WFI
|
||||||
|
|
||||||
|
#if __ARM_MEDIA__
|
||||||
|
#define __SADD8 __iar_builtin_SADD8
|
||||||
|
#define __QADD8 __iar_builtin_QADD8
|
||||||
|
#define __SHADD8 __iar_builtin_SHADD8
|
||||||
|
#define __UADD8 __iar_builtin_UADD8
|
||||||
|
#define __UQADD8 __iar_builtin_UQADD8
|
||||||
|
#define __UHADD8 __iar_builtin_UHADD8
|
||||||
|
#define __SSUB8 __iar_builtin_SSUB8
|
||||||
|
#define __QSUB8 __iar_builtin_QSUB8
|
||||||
|
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||||
|
#define __USUB8 __iar_builtin_USUB8
|
||||||
|
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||||
|
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||||
|
#define __SADD16 __iar_builtin_SADD16
|
||||||
|
#define __QADD16 __iar_builtin_QADD16
|
||||||
|
#define __SHADD16 __iar_builtin_SHADD16
|
||||||
|
#define __UADD16 __iar_builtin_UADD16
|
||||||
|
#define __UQADD16 __iar_builtin_UQADD16
|
||||||
|
#define __UHADD16 __iar_builtin_UHADD16
|
||||||
|
#define __SSUB16 __iar_builtin_SSUB16
|
||||||
|
#define __QSUB16 __iar_builtin_QSUB16
|
||||||
|
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||||
|
#define __USUB16 __iar_builtin_USUB16
|
||||||
|
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||||
|
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||||
|
#define __SASX __iar_builtin_SASX
|
||||||
|
#define __QASX __iar_builtin_QASX
|
||||||
|
#define __SHASX __iar_builtin_SHASX
|
||||||
|
#define __UASX __iar_builtin_UASX
|
||||||
|
#define __UQASX __iar_builtin_UQASX
|
||||||
|
#define __UHASX __iar_builtin_UHASX
|
||||||
|
#define __SSAX __iar_builtin_SSAX
|
||||||
|
#define __QSAX __iar_builtin_QSAX
|
||||||
|
#define __SHSAX __iar_builtin_SHSAX
|
||||||
|
#define __USAX __iar_builtin_USAX
|
||||||
|
#define __UQSAX __iar_builtin_UQSAX
|
||||||
|
#define __UHSAX __iar_builtin_UHSAX
|
||||||
|
#define __USAD8 __iar_builtin_USAD8
|
||||||
|
#define __USADA8 __iar_builtin_USADA8
|
||||||
|
#define __SSAT16 __iar_builtin_SSAT16
|
||||||
|
#define __USAT16 __iar_builtin_USAT16
|
||||||
|
#define __UXTB16 __iar_builtin_UXTB16
|
||||||
|
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||||
|
#define __SXTB16 __iar_builtin_SXTB16
|
||||||
|
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||||
|
#define __SMUAD __iar_builtin_SMUAD
|
||||||
|
#define __SMUADX __iar_builtin_SMUADX
|
||||||
|
#define __SMMLA __iar_builtin_SMMLA
|
||||||
|
#define __SMLAD __iar_builtin_SMLAD
|
||||||
|
#define __SMLADX __iar_builtin_SMLADX
|
||||||
|
#define __SMLALD __iar_builtin_SMLALD
|
||||||
|
#define __SMLALDX __iar_builtin_SMLALDX
|
||||||
|
#define __SMUSD __iar_builtin_SMUSD
|
||||||
|
#define __SMUSDX __iar_builtin_SMUSDX
|
||||||
|
#define __SMLSD __iar_builtin_SMLSD
|
||||||
|
#define __SMLSDX __iar_builtin_SMLSDX
|
||||||
|
#define __SMLSLD __iar_builtin_SMLSLD
|
||||||
|
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||||
|
#define __SEL __iar_builtin_SEL
|
||||||
|
#define __QADD __iar_builtin_QADD
|
||||||
|
#define __QSUB __iar_builtin_QSUB
|
||||||
|
#define __PKHBT __iar_builtin_PKHBT
|
||||||
|
#define __PKHTB __iar_builtin_PKHTB
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#define __CLZ __cmsis_iar_clz_not_active
|
||||||
|
#define __SSAT __cmsis_iar_ssat_not_active
|
||||||
|
#define __USAT __cmsis_iar_usat_not_active
|
||||||
|
#define __RBIT __cmsis_iar_rbit_not_active
|
||||||
|
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||||
|
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __INTRINSICS_INCLUDED
|
||||||
|
#error intrinsics.h is already included previously!
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <intrinsics.h>
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#undef __CLZ
|
||||||
|
#undef __SSAT
|
||||||
|
#undef __USAT
|
||||||
|
#undef __RBIT
|
||||||
|
#undef __get_APSR
|
||||||
|
|
||||||
|
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||||
|
{
|
||||||
|
if (data == 0U) { return 32U; }
|
||||||
|
|
||||||
|
uint32_t count = 0U;
|
||||||
|
uint32_t mask = 0x80000000U;
|
||||||
|
|
||||||
|
while ((data & mask) == 0U)
|
||||||
|
{
|
||||||
|
count += 1U;
|
||||||
|
mask = mask >> 1U;
|
||||||
|
}
|
||||||
|
return count;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||||
|
{
|
||||||
|
uint8_t sc = 31U;
|
||||||
|
uint32_t r = v;
|
||||||
|
for (v >>= 1U; v; v >>= 1U)
|
||||||
|
{
|
||||||
|
r <<= 1U;
|
||||||
|
r |= v & 1U;
|
||||||
|
sc--;
|
||||||
|
}
|
||||||
|
return (r << sc);
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm("MRS %0,APSR" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#undef __get_FPSCR
|
||||||
|
#undef __set_FPSCR
|
||||||
|
#define __get_FPSCR() (0)
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma diag_suppress=Pe940
|
||||||
|
#pragma diag_suppress=Pe177
|
||||||
|
|
||||||
|
#define __enable_irq __enable_interrupt
|
||||||
|
#define __disable_irq __disable_interrupt
|
||||||
|
#define __NOP __no_operation
|
||||||
|
|
||||||
|
#define __get_xPSR __get_PSR
|
||||||
|
|
||||||
|
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __LDREX((unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __STREX(value, (unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#undef __IAR_FT
|
||||||
|
#undef __IAR_M0_FAMILY
|
||||||
|
#undef __ICCARM_V8
|
||||||
|
|
||||||
|
#pragma diag_default=Pe940
|
||||||
|
#pragma diag_default=Pe177
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ICCARM_H__ */
|
||||||
39
Firmware/CMSIS/Core/Include/cmsis_version.h
Normal file
39
Firmware/CMSIS/Core/Include/cmsis_version.h
Normal file
@ -0,0 +1,39 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_version.h
|
||||||
|
* @brief CMSIS Core(M) Version definitions
|
||||||
|
* @version V5.0.2
|
||||||
|
* @date 19. April 2017
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CMSIS_VERSION_H
|
||||||
|
#define __CMSIS_VERSION_H
|
||||||
|
|
||||||
|
/* CMSIS Version definitions */
|
||||||
|
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||||
|
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||||
|
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||||
|
#endif
|
||||||
1918
Firmware/CMSIS/Core/Include/core_armv8mbl.h
Normal file
1918
Firmware/CMSIS/Core/Include/core_armv8mbl.h
Normal file
File diff suppressed because it is too large
Load Diff
2927
Firmware/CMSIS/Core/Include/core_armv8mml.h
Normal file
2927
Firmware/CMSIS/Core/Include/core_armv8mml.h
Normal file
File diff suppressed because it is too large
Load Diff
949
Firmware/CMSIS/Core/Include/core_cm0.h
Normal file
949
Firmware/CMSIS/Core/Include/core_cm0.h
Normal file
@ -0,0 +1,949 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm0.h
|
||||||
|
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||||
|
* @version V5.0.5
|
||||||
|
* @date 28. May 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0_H_GENERIC
|
||||||
|
#define __CORE_CM0_H_GENERIC
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\ingroup Cortex_M0
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
|
/* CMSIS CM0 definitions */
|
||||||
|
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
|
This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0U
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#if defined __ARM_PCS_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#if defined __TI_VFP_SUPPORT__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#if ( __CSMC__ & 0x400U)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0_H_DEPENDANT
|
||||||
|
#define __CORE_CM0_H_DEPENDANT
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM0_REV
|
||||||
|
#define __CM0_REV 0x0000U
|
||||||
|
#warning "__CM0_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2U
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0U
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* following defines should be used for structure members */
|
||||||
|
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||||
|
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||||
|
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M0 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
/* APSR Register Definitions */
|
||||||
|
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||||
|
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||||
|
|
||||||
|
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||||
|
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||||
|
|
||||||
|
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||||
|
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||||
|
|
||||||
|
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||||
|
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
/* IPSR Register Definitions */
|
||||||
|
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||||
|
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
/* xPSR Register Definitions */
|
||||||
|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||||
|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||||
|
|
||||||
|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||||
|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||||
|
|
||||||
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||||
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||||
|
|
||||||
|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||||
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||||
|
|
||||||
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/* CONTROL Register Definitions */
|
||||||
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||||
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31U];
|
||||||
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31U];
|
||||||
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31U];
|
||||||
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31U];
|
||||||
|
uint32_t RESERVED4[64U];
|
||||||
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||||
|
Therefore they are not covered by the Cortex-M0 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||||
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted value.
|
||||||
|
*/
|
||||||
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted bit field value.
|
||||||
|
*/
|
||||||
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Core Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Tick Configuration
|
||||||
|
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||||
|
{
|
||||||
|
return (1UL); /* Reload value impossible */
|
||||||
|
}
|
||||||
|
|
||||||
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0UL); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
||||||
1083
Firmware/CMSIS/Core/Include/core_cm0plus.h
Normal file
1083
Firmware/CMSIS/Core/Include/core_cm0plus.h
Normal file
File diff suppressed because it is too large
Load Diff
976
Firmware/CMSIS/Core/Include/core_cm1.h
Normal file
976
Firmware/CMSIS/Core/Include/core_cm1.h
Normal file
@ -0,0 +1,976 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm1.h
|
||||||
|
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||||
|
* @version V1.0.0
|
||||||
|
* @date 23. July 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_GENERIC
|
||||||
|
#define __CORE_CM1_H_GENERIC
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\ingroup Cortex_M1
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
|
/* CMSIS CM1 definitions */
|
||||||
|
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
|
This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0U
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#if defined __ARM_PCS_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#if defined __TI_VFP_SUPPORT__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#if ( __CSMC__ & 0x400U)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_DEPENDANT
|
||||||
|
#define __CORE_CM1_H_DEPENDANT
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM1_REV
|
||||||
|
#define __CM1_REV 0x0100U
|
||||||
|
#warning "__CM1_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2U
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0U
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* following defines should be used for structure members */
|
||||||
|
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||||
|
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||||
|
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M1 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
/* APSR Register Definitions */
|
||||||
|
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||||
|
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||||
|
|
||||||
|
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||||
|
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||||
|
|
||||||
|
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||||
|
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||||
|
|
||||||
|
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||||
|
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
/* IPSR Register Definitions */
|
||||||
|
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||||
|
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
/* xPSR Register Definitions */
|
||||||
|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||||
|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||||
|
|
||||||
|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||||
|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||||
|
|
||||||
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||||
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||||
|
|
||||||
|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||||
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||||
|
|
||||||
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/* CONTROL Register Definitions */
|
||||||
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||||
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31U];
|
||||||
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31U];
|
||||||
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31U];
|
||||||
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31U];
|
||||||
|
uint32_t RESERVED4[64U];
|
||||||
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||||
|
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0[2U];
|
||||||
|
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||||
|
} SCnSCB_Type;
|
||||||
|
|
||||||
|
/* Auxiliary Control Register Definitions */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||||
|
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCnotSCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||||
|
Therefore they are not covered by the Cortex-M1 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||||
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted value.
|
||||||
|
*/
|
||||||
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted bit field value.
|
||||||
|
*/
|
||||||
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Core Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Tick Configuration
|
||||||
|
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||||
|
{
|
||||||
|
return (1UL); /* Reload value impossible */
|
||||||
|
}
|
||||||
|
|
||||||
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0UL); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
||||||
1993
Firmware/CMSIS/Core/Include/core_cm23.h
Normal file
1993
Firmware/CMSIS/Core/Include/core_cm23.h
Normal file
File diff suppressed because it is too large
Load Diff
1941
Firmware/CMSIS/Core/Include/core_cm3.h
Normal file
1941
Firmware/CMSIS/Core/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
3002
Firmware/CMSIS/Core/Include/core_cm33.h
Normal file
3002
Firmware/CMSIS/Core/Include/core_cm33.h
Normal file
File diff suppressed because it is too large
Load Diff
2129
Firmware/CMSIS/Core/Include/core_cm4.h
Normal file
2129
Firmware/CMSIS/Core/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2671
Firmware/CMSIS/Core/Include/core_cm7.h
Normal file
2671
Firmware/CMSIS/Core/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
1022
Firmware/CMSIS/Core/Include/core_sc000.h
Normal file
1022
Firmware/CMSIS/Core/Include/core_sc000.h
Normal file
File diff suppressed because it is too large
Load Diff
1915
Firmware/CMSIS/Core/Include/core_sc300.h
Normal file
1915
Firmware/CMSIS/Core/Include/core_sc300.h
Normal file
File diff suppressed because it is too large
Load Diff
270
Firmware/CMSIS/Core/Include/mpu_armv7.h
Normal file
270
Firmware/CMSIS/Core/Include/mpu_armv7.h
Normal file
@ -0,0 +1,270 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv7.h
|
||||||
|
* @brief CMSIS MPU API for Armv7-M MPU
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV7_H
|
||||||
|
#define ARM_MPU_ARMV7_H
|
||||||
|
|
||||||
|
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||||
|
|
||||||
|
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||||
|
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||||
|
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||||
|
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||||
|
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||||
|
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||||
|
|
||||||
|
/** MPU Region Base Address Register Value
|
||||||
|
*
|
||||||
|
* \param Region The region to be configured, number 0 to 15.
|
||||||
|
* \param BaseAddress The base address for the region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||||
|
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||||
|
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||||
|
(MPU_RBAR_VALID_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attributes
|
||||||
|
*
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||||
|
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||||
|
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||||
|
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||||
|
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||||
|
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||||
|
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||||
|
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||||
|
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for strongly ordered memory.
|
||||||
|
* - TEX: 000b
|
||||||
|
* - Shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Non-bufferable
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for device memory.
|
||||||
|
* - TEX: 000b (if non-shareable) or 010b (if shareable)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||||
|
*
|
||||||
|
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for normal memory.
|
||||||
|
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||||
|
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||||
|
*
|
||||||
|
* \param OuterCp Configures the outer cache policy.
|
||||||
|
* \param InnerCp Configures the inner cache policy.
|
||||||
|
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute non-cacheable policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||||
|
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RASR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure an MPU region.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
while (cnt > MPU_TYPE_RALIASES) {
|
||||||
|
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||||
|
table += MPU_TYPE_RALIASES;
|
||||||
|
cnt -= MPU_TYPE_RALIASES;
|
||||||
|
}
|
||||||
|
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
333
Firmware/CMSIS/Core/Include/mpu_armv8.h
Normal file
333
Firmware/CMSIS/Core/Include/mpu_armv8.h
Normal file
@ -0,0 +1,333 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv8.h
|
||||||
|
* @brief CMSIS MPU API for Armv8-M MPU
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV8_H
|
||||||
|
#define ARM_MPU_ARMV8_H
|
||||||
|
|
||||||
|
/** \brief Attribute for device memory (outer only) */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||||
|
|
||||||
|
/** \brief Attribute for non-cacheable, normal memory */
|
||||||
|
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||||
|
|
||||||
|
/** \brief Attribute for normal memory (outer and inner)
|
||||||
|
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||||
|
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||||
|
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||||
|
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||||
|
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||||
|
|
||||||
|
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||||
|
|
||||||
|
/** \brief Memory Attribute
|
||||||
|
* \param O Outer memory attributes
|
||||||
|
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||||
|
|
||||||
|
/** \brief Normal memory non-shareable */
|
||||||
|
#define ARM_MPU_SH_NON (0U)
|
||||||
|
|
||||||
|
/** \brief Normal memory outer shareable */
|
||||||
|
#define ARM_MPU_SH_OUTER (2U)
|
||||||
|
|
||||||
|
/** \brief Normal memory inner shareable */
|
||||||
|
#define ARM_MPU_SH_INNER (3U)
|
||||||
|
|
||||||
|
/** \brief Memory access permissions
|
||||||
|
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||||
|
|
||||||
|
/** \brief Region Base Address Register value
|
||||||
|
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||||
|
* \param SH Defines the Shareability domain for this memory region.
|
||||||
|
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||||
|
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||||
|
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||||
|
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||||
|
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||||
|
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||||
|
|
||||||
|
/** \brief Region Limit Address Register value
|
||||||
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||||
|
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||||
|
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||||
|
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Enable the Non-secure MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the Non-secure MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU to be configured.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
const uint8_t reg = idx / 4U;
|
||||||
|
const uint32_t pos = ((idx % 4U) * 8U);
|
||||||
|
const uint32_t mask = 0xFFU << pos;
|
||||||
|
|
||||||
|
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||||
|
return; // invalid index
|
||||||
|
}
|
||||||
|
|
||||||
|
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RLAR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Clear and disable the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Configure the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RBAR = rbar;
|
||||||
|
mpu->RLAR = rlar;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Configure the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU registers to be used.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
if (cnt == 1U) {
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||||
|
} else {
|
||||||
|
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||||
|
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||||
|
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||||
|
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||||
|
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||||
|
table += c;
|
||||||
|
cnt -= c;
|
||||||
|
rnrOffset = 0U;
|
||||||
|
rnrBase += MPU_TYPE_RALIASES;
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
}
|
||||||
|
|
||||||
|
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
70
Firmware/CMSIS/Core/Include/tz_context.h
Normal file
70
Firmware/CMSIS/Core/Include/tz_context.h
Normal file
@ -0,0 +1,70 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file tz_context.h
|
||||||
|
* @brief Context Management for Armv8-M TrustZone
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef TZ_CONTEXT_H
|
||||||
|
#define TZ_CONTEXT_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifndef TZ_MODULEID_T
|
||||||
|
#define TZ_MODULEID_T
|
||||||
|
/// \details Data type that identifies secure software modules called by a process.
|
||||||
|
typedef uint32_t TZ_ModuleId_t;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||||
|
typedef uint32_t TZ_MemoryId_t;
|
||||||
|
|
||||||
|
/// Initialize secure context memory system
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_InitContextSystem_S (void);
|
||||||
|
|
||||||
|
/// Allocate context memory for calling secure software modules in TrustZone
|
||||||
|
/// \param[in] module identifies software modules called from non-secure mode
|
||||||
|
/// \return value != 0 id TrustZone memory slot identifier
|
||||||
|
/// \return value 0 no memory available or internal error
|
||||||
|
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||||
|
|
||||||
|
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Load secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Store secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
#endif // TZ_CONTEXT_H
|
||||||
196
Firmware/CMSIS/Documentation/Core/html/index.html
Normal file
196
Firmware/CMSIS/Documentation/Core/html/index.html
Normal file
@ -0,0 +1,196 @@
|
|||||||
|
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||||
|
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||||
|
<head>
|
||||||
|
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
|
||||||
|
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
|
||||||
|
<title>Overview</title>
|
||||||
|
<title>CMSIS-Core (Cortex-M): Overview</title>
|
||||||
|
<link href="tabs.css" rel="stylesheet" type="text/css"/>
|
||||||
|
<link href="cmsis.css" rel="stylesheet" type="text/css" />
|
||||||
|
<script type="text/javascript" src="jquery.js"></script>
|
||||||
|
<script type="text/javascript" src="dynsections.js"></script>
|
||||||
|
<script type="text/javascript" src="printComponentTabs.js"></script>
|
||||||
|
<link href="navtree.css" rel="stylesheet" type="text/css"/>
|
||||||
|
<script type="text/javascript" src="resize.js"></script>
|
||||||
|
<script type="text/javascript" src="navtree.js"></script>
|
||||||
|
<script type="text/javascript">
|
||||||
|
$(document).ready(initResizable);
|
||||||
|
$(window).load(resizeHeight);
|
||||||
|
</script>
|
||||||
|
<link href="search/search.css" rel="stylesheet" type="text/css"/>
|
||||||
|
<script type="text/javascript" src="search/search.js"></script>
|
||||||
|
<script type="text/javascript">
|
||||||
|
$(document).ready(function() { searchBox.OnSelectItem(0); });
|
||||||
|
</script>
|
||||||
|
</head>
|
||||||
|
<body>
|
||||||
|
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
|
||||||
|
<div id="titlearea">
|
||||||
|
<table cellspacing="0" cellpadding="0">
|
||||||
|
<tbody>
|
||||||
|
<tr style="height: 46px;">
|
||||||
|
<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
|
||||||
|
<td style="padding-left: 0.5em;">
|
||||||
|
<div id="projectname">CMSIS-Core (Cortex-M)
|
||||||
|
 <span id="projectnumber">Version 5.1.2</span>
|
||||||
|
</div>
|
||||||
|
<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
|
||||||
|
</td>
|
||||||
|
</tr>
|
||||||
|
</tbody>
|
||||||
|
</table>
|
||||||
|
</div>
|
||||||
|
<!-- end header part -->
|
||||||
|
<div id="CMSISnav" class="tabs1">
|
||||||
|
<ul class="tablist">
|
||||||
|
<script type="text/javascript">
|
||||||
|
<!--
|
||||||
|
writeComponentTabs.call(this);
|
||||||
|
//-->
|
||||||
|
</script>
|
||||||
|
</ul>
|
||||||
|
</div>
|
||||||
|
<!-- Generated by Doxygen 1.8.6 -->
|
||||||
|
<script type="text/javascript">
|
||||||
|
var searchBox = new SearchBox("searchBox", "search",false,'Search');
|
||||||
|
</script>
|
||||||
|
<div id="navrow1" class="tabs">
|
||||||
|
<ul class="tablist">
|
||||||
|
<li class="current"><a href="index.html"><span>Main Page</span></a></li>
|
||||||
|
<li><a href="pages.html"><span>Usage and Description</span></a></li>
|
||||||
|
<li><a href="modules.html"><span>Reference</span></a></li>
|
||||||
|
<li>
|
||||||
|
<div id="MSearchBox" class="MSearchBoxInactive">
|
||||||
|
<span class="left">
|
||||||
|
<img id="MSearchSelect" src="search/mag_sel.png"
|
||||||
|
onmouseover="return searchBox.OnSearchSelectShow()"
|
||||||
|
onmouseout="return searchBox.OnSearchSelectHide()"
|
||||||
|
alt=""/>
|
||||||
|
<input type="text" id="MSearchField" value="Search" accesskey="S"
|
||||||
|
onfocus="searchBox.OnSearchFieldFocus(true)"
|
||||||
|
onblur="searchBox.OnSearchFieldFocus(false)"
|
||||||
|
onkeyup="searchBox.OnSearchFieldChange(event)"/>
|
||||||
|
</span><span class="right">
|
||||||
|
<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
|
||||||
|
</span>
|
||||||
|
</div>
|
||||||
|
</li>
|
||||||
|
</ul>
|
||||||
|
</div>
|
||||||
|
</div><!-- top -->
|
||||||
|
<div id="side-nav" class="ui-resizable side-nav-resizable">
|
||||||
|
<div id="nav-tree">
|
||||||
|
<div id="nav-tree-contents">
|
||||||
|
<div id="nav-sync" class="sync"></div>
|
||||||
|
</div>
|
||||||
|
</div>
|
||||||
|
<div id="splitbar" style="-moz-user-select:none;"
|
||||||
|
class="ui-resizable-handle">
|
||||||
|
</div>
|
||||||
|
</div>
|
||||||
|
<script type="text/javascript">
|
||||||
|
$(document).ready(function(){initNavTree('index.html','');});
|
||||||
|
</script>
|
||||||
|
<div id="doc-content">
|
||||||
|
<!-- window showing the filter options -->
|
||||||
|
<div id="MSearchSelectWindow"
|
||||||
|
onmouseover="return searchBox.OnSearchSelectShow()"
|
||||||
|
onmouseout="return searchBox.OnSearchSelectHide()"
|
||||||
|
onkeydown="return searchBox.OnSearchSelectKey(event)">
|
||||||
|
<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
|
||||||
|
|
||||||
|
<!-- iframe showing the search results (closed by default) -->
|
||||||
|
<div id="MSearchResultsWindow">
|
||||||
|
<iframe src="javascript:void(0)" frameborder="0"
|
||||||
|
name="MSearchResults" id="MSearchResults">
|
||||||
|
</iframe>
|
||||||
|
</div>
|
||||||
|
|
||||||
|
<div class="header">
|
||||||
|
<div class="headertitle">
|
||||||
|
<div class="title">Overview </div> </div>
|
||||||
|
</div><!--header-->
|
||||||
|
<div class="contents">
|
||||||
|
<div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
|
||||||
|
<ul>
|
||||||
|
<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
|
||||||
|
<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
|
||||||
|
<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
|
||||||
|
<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
|
||||||
|
<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
|
||||||
|
<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
|
||||||
|
</ul>
|
||||||
|
<p>The following sections provide details about the CMSIS-Core (Cortex-M):</p>
|
||||||
|
<ul>
|
||||||
|
<li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
|
||||||
|
<li><a class="el" href="using_TrustZone_pg.html">Using TrustZone® for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture.</li>
|
||||||
|
<li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
|
||||||
|
<li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
|
||||||
|
<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
|
||||||
|
<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
|
||||||
|
</ul>
|
||||||
|
<hr/>
|
||||||
|
<h2>CMSIS-Core (Cortex-M) in ARM::CMSIS Pack </h2>
|
||||||
|
<p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p>
|
||||||
|
<table class="doxtable">
|
||||||
|
<tr>
|
||||||
|
<th>File/Folder </th><th>Content </th></tr>
|
||||||
|
<tr>
|
||||||
|
<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
|
||||||
|
<tr>
|
||||||
|
<td><b>CMSIS\Core\Include</b> </td><td>CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
|
||||||
|
<tr>
|
||||||
|
<td><b>Device</b> </td><td><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices </td></tr>
|
||||||
|
<tr>
|
||||||
|
<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors </td></tr>
|
||||||
|
</table>
|
||||||
|
<hr/>
|
||||||
|
<h1><a class="anchor" id="ref_v6-v8M"></a>
|
||||||
|
Processor Support</h1>
|
||||||
|
<p>CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.</p>
|
||||||
|
<h2><a class="anchor" id="ref_man_sec"></a>
|
||||||
|
Cortex-M Reference Manuals</h2>
|
||||||
|
<p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p>
|
||||||
|
<ul>
|
||||||
|
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
|
||||||
|
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
|
||||||
|
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
|
||||||
|
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)</li>
|
||||||
|
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
|
||||||
|
</ul>
|
||||||
|
<p>The <b>Cortex-M23</b> and <b>Cortex-M33</b> are described with Technical Reference Manuals that are available here:</p>
|
||||||
|
<ul>
|
||||||
|
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)</li>
|
||||||
|
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)</li>
|
||||||
|
</ul>
|
||||||
|
<h2><a class="anchor" id="ARMv8M"></a>
|
||||||
|
Armv8-M Architecture</h2>
|
||||||
|
<p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.</p>
|
||||||
|
<p>The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p>
|
||||||
|
<hr/>
|
||||||
|
<h1><a class="anchor" id="tested_tools_sec"></a>
|
||||||
|
Tested and Verified Toolchains</h1>
|
||||||
|
<p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p>
|
||||||
|
<ul>
|
||||||
|
<li>Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)</li>
|
||||||
|
<li>Arm: Arm Compiler 6.9</li>
|
||||||
|
<li>Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)</li>
|
||||||
|
<li>GNU: GNU Tools for Arm Embedded 6.3.1 20170620</li>
|
||||||
|
<li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183</li>
|
||||||
|
</ul>
|
||||||
|
<hr/>
|
||||||
|
</div></div><!-- contents -->
|
||||||
|
</div><!-- doc-content -->
|
||||||
|
<!-- start footer part -->
|
||||||
|
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||||
|
<ul>
|
||||||
|
<li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved.
|
||||||
|
<!--
|
||||||
|
<a href="http://www.doxygen.org/index.html">
|
||||||
|
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6
|
||||||
|
-->
|
||||||
|
</li>
|
||||||
|
</ul>
|
||||||
|
</div>
|
||||||
|
</body>
|
||||||
|
</html>
|
||||||
29
Firmware/Makefile
Normal file
29
Firmware/Makefile
Normal file
@ -0,0 +1,29 @@
|
|||||||
|
OBJS += \
|
||||||
|
leds.o \
|
||||||
|
animation.o
|
||||||
|
|
||||||
|
OBJS_AS_ARGS += \
|
||||||
|
"leds.o" \
|
||||||
|
"animation.o"
|
||||||
|
|
||||||
|
DEPS_AS_ARGS += \
|
||||||
|
"leds.d" \
|
||||||
|
"animation.d"
|
||||||
|
|
||||||
|
export
|
||||||
|
|
||||||
|
build:
|
||||||
|
@$(MAKE) -C gcc
|
||||||
|
|
||||||
|
install: build
|
||||||
|
@openocd -f "openocd.cfg" \
|
||||||
|
-c "program ./gcc/AtmelStart.elf verify reset exit"
|
||||||
|
|
||||||
|
run: flash
|
||||||
|
@openocd -f openocd.cfg
|
||||||
|
@arm-none-eabi-gdb -e ./gdbinit
|
||||||
|
|
||||||
|
clean:
|
||||||
|
@$(MAKE) clean -C gcc
|
||||||
|
|
||||||
|
.PHONY: build flash debug clean
|
||||||
20
Firmware/animation.c
Normal file
20
Firmware/animation.c
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
#include "animation.h"
|
||||||
|
#include <utils_list.h>
|
||||||
|
|
||||||
|
static struct list_descriptor animations;
|
||||||
|
|
||||||
|
void animation_init() {
|
||||||
|
list_reset(&animations);
|
||||||
|
// init callbacks
|
||||||
|
}
|
||||||
|
|
||||||
|
void animation_append(struct animation *anim) {
|
||||||
|
if (animations.head == NULL)
|
||||||
|
list_insert_as_head(&animations, anim);
|
||||||
|
else
|
||||||
|
list_insert_at_end(&animations, anim);
|
||||||
|
}
|
||||||
|
|
||||||
|
void animation_remove(struct animation *anim) {
|
||||||
|
list_delete_element(&animations, anim);
|
||||||
|
}
|
||||||
21
Firmware/animation.h
Normal file
21
Firmware/animation.h
Normal file
@ -0,0 +1,21 @@
|
|||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
struct animation_state
|
||||||
|
{
|
||||||
|
uint8_t size;
|
||||||
|
uint8_t *data;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct animation
|
||||||
|
{
|
||||||
|
struct animation *next;
|
||||||
|
void (*init) (struct animation_state state);
|
||||||
|
void (*loop) (struct animation_state state);
|
||||||
|
uint32_t intervall;
|
||||||
|
};
|
||||||
|
|
||||||
|
void animation_init ();
|
||||||
|
void animation_new (struct animation *anim);
|
||||||
|
void animation_append (struct animation *anim);
|
||||||
|
void animation_remove (struct animation *anim);
|
||||||
|
|
||||||
213
Firmware/armcc/Device/SAMD09/Source/ARM/startup_SAMD09.s
Normal file
213
Firmware/armcc/Device/SAMD09/Source/ARM/startup_SAMD09.s
Normal file
@ -0,0 +1,213 @@
|
|||||||
|
;/*****************************************************************************
|
||||||
|
; * @file startup_SAMD09.s
|
||||||
|
; * @brief CMSIS Cortex-M0+ Core Device Startup File
|
||||||
|
; * for the Atmel SAMD09 Device Series
|
||||||
|
; * @version V1.00
|
||||||
|
; * @date 25. August 2015
|
||||||
|
; *
|
||||||
|
; * @note
|
||||||
|
; * Copyright (C) 2015 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; ******************************************************************************/
|
||||||
|
;/*
|
||||||
|
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||||
|
;*/
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000000
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD PM_Handler ; 0 Power Manager
|
||||||
|
DCD SYSCTRL_Handler ; 1 System Control
|
||||||
|
DCD WDT_Handler ; 2 Watchdog Timer
|
||||||
|
DCD RTC_Handler ; 3 Real-Time Counter
|
||||||
|
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||||
|
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||||
|
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||||
|
DCD USB_Handler ; 7 Universal Serial Bus
|
||||||
|
DCD EVSYS_Handler ; 8 Event System Interface
|
||||||
|
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||||
|
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||||
|
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||||
|
DCD 0 ; 12 Reserved
|
||||||
|
DCD TC1_Handler ; 13 Basic Timer Counter 0
|
||||||
|
DCD TC2_Handler ; 14 Basic Timer Counter 1
|
||||||
|
DCD ADC_Handler ; 15 Analog Digital Converter
|
||||||
|
DCD 0 ; 16 Reserved
|
||||||
|
DCD DAC_Handler ; 17 Digital Analog Converter
|
||||||
|
DCD PTC_Handle ; 18 Peripheral Touch Controller
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT SYSCTRL_Handler [WEAK]
|
||||||
|
EXPORT WDT_Handler [WEAK]
|
||||||
|
EXPORT RTC_Handler [WEAK]
|
||||||
|
EXPORT EIC_Handler [WEAK]
|
||||||
|
EXPORT NVMCTRL_Handler [WEAK]
|
||||||
|
EXPORT DMAC_Handler [WEAK]
|
||||||
|
EXPORT USB_Handler [WEAK]
|
||||||
|
EXPORT EVSYS_Handler [WEAK]
|
||||||
|
EXPORT SERCOM0_Handler [WEAK]
|
||||||
|
EXPORT SERCOM1_Handler [WEAK]
|
||||||
|
EXPORT SERCOM2_Handler [WEAK]
|
||||||
|
EXPORT TC1_Handler [WEAK]
|
||||||
|
EXPORT TC2_Handler [WEAK]
|
||||||
|
EXPORT ADC_Handler [WEAK]
|
||||||
|
EXPORT DAC_Handler [WEAK]
|
||||||
|
EXPORT PTC_Handle [WEAK]
|
||||||
|
|
||||||
|
PM_Handler
|
||||||
|
SYSCTRL_Handler
|
||||||
|
WDT_Handler
|
||||||
|
RTC_Handler
|
||||||
|
EIC_Handler
|
||||||
|
NVMCTRL_Handler
|
||||||
|
DMAC_Handler
|
||||||
|
USB_Handler
|
||||||
|
EVSYS_Handler
|
||||||
|
SERCOM0_Handler
|
||||||
|
SERCOM1_Handler
|
||||||
|
SERCOM2_Handler
|
||||||
|
TC1_Handler
|
||||||
|
TC2_Handler
|
||||||
|
ADC_Handler
|
||||||
|
DAC_Handler
|
||||||
|
PTC_Handle
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
|
||||||
|
; User Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
|
||||||
|
END
|
||||||
78
Firmware/armcc/Device/SAMD09/Source/system_samd09.c
Normal file
78
Firmware/armcc/Device/SAMD09/Source/system_samd09.c
Normal file
@ -0,0 +1,78 @@
|
|||||||
|
/**
|
||||||
|
* \file
|
||||||
|
*
|
||||||
|
* \brief Low-level initialization functions called upon chip startup.
|
||||||
|
*
|
||||||
|
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||||
|
*
|
||||||
|
* \asf_license_start
|
||||||
|
*
|
||||||
|
* \page License
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||||
|
* from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* 4. This software may only be redistributed and used in connection with an
|
||||||
|
* Atmel microcontroller product.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||||
|
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||||
|
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||||
|
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* \asf_license_stop
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "samd09.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||||
|
* the source for the main clock at chip startup.
|
||||||
|
*/
|
||||||
|
#define __SYSTEM_CLOCK (1000000)
|
||||||
|
|
||||||
|
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initialize the system
|
||||||
|
*
|
||||||
|
* @brief Setup the microcontroller system.
|
||||||
|
* Initialize the System and update the SystemCoreClock variable.
|
||||||
|
*/
|
||||||
|
void SystemInit(void)
|
||||||
|
{
|
||||||
|
// Keep the default device state after reset
|
||||||
|
SystemCoreClock = __SYSTEM_CLOCK;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Update SystemCoreClock variable
|
||||||
|
*
|
||||||
|
* @brief Updates the SystemCoreClock with current core Clock
|
||||||
|
* retrieved from cpu registers.
|
||||||
|
*/
|
||||||
|
void SystemCoreClockUpdate(void)
|
||||||
|
{
|
||||||
|
// Not implemented
|
||||||
|
SystemCoreClock = __SYSTEM_CLOCK;
|
||||||
|
return;
|
||||||
|
}
|
||||||
217
Firmware/armcc/Makefile
Normal file
217
Firmware/armcc/Makefile
Normal file
@ -0,0 +1,217 @@
|
|||||||
|
|
||||||
|
################################################################################
|
||||||
|
# Automatically-generated file. Do not edit!
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
ifdef SystemRoot
|
||||||
|
SHELL = cmd.exe
|
||||||
|
MK_DIR = mkdir
|
||||||
|
else
|
||||||
|
ifeq ($(shell uname), Linux)
|
||||||
|
MK_DIR = mkdir -p
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
|
||||||
|
MK_DIR = mkdir -p
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
|
||||||
|
MK_DIR = mkdir -p
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
|
||||||
|
MK_DIR = mkdir -p
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
# List the subdirectories for creating object files
|
||||||
|
SUB_DIRS += \
|
||||||
|
\
|
||||||
|
hpl/adc \
|
||||||
|
armcc/Device/SAMD09/Source/ARM \
|
||||||
|
hpl/systick \
|
||||||
|
hpl/dmac \
|
||||||
|
hal/src \
|
||||||
|
hal/utils/src \
|
||||||
|
hpl/pm \
|
||||||
|
hpl/sysctrl \
|
||||||
|
hpl/eic \
|
||||||
|
examples \
|
||||||
|
hpl/gclk \
|
||||||
|
hpl/wdt \
|
||||||
|
hpl/rtc \
|
||||||
|
armcc/Device/SAMD09/Source \
|
||||||
|
hpl/core
|
||||||
|
|
||||||
|
# List the object files
|
||||||
|
OBJS += \
|
||||||
|
hal/src/hal_io.o \
|
||||||
|
hpl/systick/hpl_systick.o \
|
||||||
|
armcc/Device/SAMD09/Source/system_samd09.o \
|
||||||
|
hpl/wdt/hpl_wdt.o \
|
||||||
|
hpl/eic/hpl_eic.o \
|
||||||
|
hal/src/hal_timer.o \
|
||||||
|
hal/src/hal_delay.o \
|
||||||
|
hpl/sysctrl/hpl_sysctrl.o \
|
||||||
|
hpl/core/hpl_init.o \
|
||||||
|
hal/src/hal_wdt.o \
|
||||||
|
hpl/core/hpl_core_m0plus_base.o \
|
||||||
|
hal/utils/src/utils_assert.o \
|
||||||
|
hpl/dmac/hpl_dmac.o \
|
||||||
|
hpl/pm/hpl_pm.o \
|
||||||
|
hpl/gclk/hpl_gclk.o \
|
||||||
|
hal/src/hal_init.o \
|
||||||
|
main.o \
|
||||||
|
hal/utils/src/utils_list.o \
|
||||||
|
hpl/rtc/hpl_rtc.o \
|
||||||
|
examples/driver_examples.o \
|
||||||
|
driver_init.o \
|
||||||
|
hal/src/hal_adc_sync.o \
|
||||||
|
hal/src/hal_ext_irq.o \
|
||||||
|
armcc/Device/SAMD09/Source/ARM/startup_SAMD09.o \
|
||||||
|
hal/src/hal_gpio.o \
|
||||||
|
hal/utils/src/utils_event.o \
|
||||||
|
hal/src/hal_sleep.o \
|
||||||
|
atmel_start.o \
|
||||||
|
hal/src/hal_atomic.o \
|
||||||
|
hpl/adc/hpl_adc.o
|
||||||
|
|
||||||
|
OBJS_AS_ARGS += \
|
||||||
|
"hal/src/hal_io.o" \
|
||||||
|
"hpl/systick/hpl_systick.o" \
|
||||||
|
"armcc/Device/SAMD09/Source/system_samd09.o" \
|
||||||
|
"hpl/wdt/hpl_wdt.o" \
|
||||||
|
"hpl/eic/hpl_eic.o" \
|
||||||
|
"hal/src/hal_timer.o" \
|
||||||
|
"hal/src/hal_delay.o" \
|
||||||
|
"hpl/sysctrl/hpl_sysctrl.o" \
|
||||||
|
"hpl/core/hpl_init.o" \
|
||||||
|
"hal/src/hal_wdt.o" \
|
||||||
|
"hpl/core/hpl_core_m0plus_base.o" \
|
||||||
|
"hal/utils/src/utils_assert.o" \
|
||||||
|
"hpl/dmac/hpl_dmac.o" \
|
||||||
|
"hpl/pm/hpl_pm.o" \
|
||||||
|
"hpl/gclk/hpl_gclk.o" \
|
||||||
|
"hal/src/hal_init.o" \
|
||||||
|
"main.o" \
|
||||||
|
"hal/utils/src/utils_list.o" \
|
||||||
|
"hpl/rtc/hpl_rtc.o" \
|
||||||
|
"examples/driver_examples.o" \
|
||||||
|
"driver_init.o" \
|
||||||
|
"hal/src/hal_adc_sync.o" \
|
||||||
|
"hal/src/hal_ext_irq.o" \
|
||||||
|
"armcc/Device/SAMD09/Source/ARM/startup_SAMD09.o" \
|
||||||
|
"hal/src/hal_gpio.o" \
|
||||||
|
"hal/utils/src/utils_event.o" \
|
||||||
|
"hal/src/hal_sleep.o" \
|
||||||
|
"atmel_start.o" \
|
||||||
|
"hal/src/hal_atomic.o" \
|
||||||
|
"hpl/adc/hpl_adc.o"
|
||||||
|
|
||||||
|
# List the dependency files
|
||||||
|
DEPS := $(OBJS:%.o=%.d)
|
||||||
|
|
||||||
|
DEPS_AS_ARGS += \
|
||||||
|
"hpl/wdt/hpl_wdt.d" \
|
||||||
|
"armcc/Device/SAMD09/Source/system_samd09.d" \
|
||||||
|
"hal/utils/src/utils_event.d" \
|
||||||
|
"hal/src/hal_io.d" \
|
||||||
|
"hpl/systick/hpl_systick.d" \
|
||||||
|
"hpl/eic/hpl_eic.d" \
|
||||||
|
"hal/src/hal_timer.d" \
|
||||||
|
"hpl/core/hpl_core_m0plus_base.d" \
|
||||||
|
"hal/src/hal_wdt.d" \
|
||||||
|
"hpl/dmac/hpl_dmac.d" \
|
||||||
|
"hal/utils/src/utils_assert.d" \
|
||||||
|
"hal/src/hal_delay.d" \
|
||||||
|
"hpl/core/hpl_init.d" \
|
||||||
|
"hpl/sysctrl/hpl_sysctrl.d" \
|
||||||
|
"hpl/gclk/hpl_gclk.d" \
|
||||||
|
"hal/src/hal_init.d" \
|
||||||
|
"driver_init.d" \
|
||||||
|
"hal/src/hal_adc_sync.d" \
|
||||||
|
"main.d" \
|
||||||
|
"examples/driver_examples.d" \
|
||||||
|
"hpl/rtc/hpl_rtc.d" \
|
||||||
|
"hal/utils/src/utils_list.d" \
|
||||||
|
"hal/src/hal_sleep.d" \
|
||||||
|
"hal/src/hal_ext_irq.d" \
|
||||||
|
"hal/src/hal_gpio.d" \
|
||||||
|
"armcc/Device/SAMD09/Source/ARM/startup_SAMD09.d" \
|
||||||
|
"hal/src/hal_atomic.d" \
|
||||||
|
"hpl/pm/hpl_pm.d" \
|
||||||
|
"hpl/adc/hpl_adc.d" \
|
||||||
|
"atmel_start.d"
|
||||||
|
|
||||||
|
OUTPUT_FILE_NAME :=AtmelStart
|
||||||
|
QUOTE := "
|
||||||
|
OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
|
||||||
|
OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
|
||||||
|
|
||||||
|
vpath %.c ../
|
||||||
|
vpath %.s ../
|
||||||
|
vpath %.S ../
|
||||||
|
|
||||||
|
# All Target
|
||||||
|
all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
|
||||||
|
|
||||||
|
# Linker target
|
||||||
|
|
||||||
|
$(OUTPUT_FILE_PATH): $(OBJS)
|
||||||
|
@echo Building target: $@
|
||||||
|
@echo Invoking: ARMCC Linker
|
||||||
|
$(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \
|
||||||
|
--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \
|
||||||
|
--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \
|
||||||
|
-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M0+ \
|
||||||
|
$(OBJS_AS_ARGS)
|
||||||
|
|
||||||
|
@echo Finished building target: $@
|
||||||
|
|
||||||
|
# Compiler target(s)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
%.o: %.c
|
||||||
|
@echo Building file: $<
|
||||||
|
@echo ARMCC Compiler
|
||||||
|
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD09C13A__ \
|
||||||
|
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/wdt" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||||
|
--depend "$@" -o "$@" "$<"
|
||||||
|
|
||||||
|
@echo Finished building: $<
|
||||||
|
|
||||||
|
%.o: %.s
|
||||||
|
@echo Building file: $<
|
||||||
|
@echo ARMCC Assembler
|
||||||
|
$(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M0+ --pd "D__SAMD09C13A__ SETA 1" \
|
||||||
|
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/wdt" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||||
|
--depend "$(@:%.o=%.d)" -o "$@" "$<"
|
||||||
|
|
||||||
|
@echo Finished building: $<
|
||||||
|
|
||||||
|
%.o: %.S
|
||||||
|
@echo Building file: $<
|
||||||
|
@echo ARMCC Preprocessing Assembler
|
||||||
|
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD09C13A__ \
|
||||||
|
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/wdt" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||||
|
--depend "$@" -o "$@" "$<"
|
||||||
|
|
||||||
|
@echo Finished building: $<
|
||||||
|
|
||||||
|
# Detect changes in the dependent files and recompile the respective object files.
|
||||||
|
ifneq ($(MAKECMDGOALS),clean)
|
||||||
|
ifneq ($(strip $(DEPS)),)
|
||||||
|
-include $(DEPS)
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(SUB_DIRS):
|
||||||
|
$(MK_DIR) "$@"
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(OBJS_AS_ARGS)
|
||||||
|
rm -f $(OUTPUT_FILE_PATH)
|
||||||
|
rm -f $(DEPS_AS_ARGS)
|
||||||
|
rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf
|
||||||
9
Firmware/atmel_start.c
Normal file
9
Firmware/atmel_start.c
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
#include <atmel_start.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initializes MCU, drivers and middleware in the project
|
||||||
|
**/
|
||||||
|
void atmel_start_init(void)
|
||||||
|
{
|
||||||
|
system_init();
|
||||||
|
}
|
||||||
18
Firmware/atmel_start.h
Normal file
18
Firmware/atmel_start.h
Normal file
@ -0,0 +1,18 @@
|
|||||||
|
#ifndef ATMEL_START_H_INCLUDED
|
||||||
|
#define ATMEL_START_H_INCLUDED
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "driver_init.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initializes MCU, drivers and middleware in the project
|
||||||
|
**/
|
||||||
|
void atmel_start_init(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
691
Firmware/atmel_start_config.atstart
Normal file
691
Firmware/atmel_start_config.atstart
Normal file
@ -0,0 +1,691 @@
|
|||||||
|
format_version: '2'
|
||||||
|
name: My Project
|
||||||
|
versions:
|
||||||
|
api: '1.0'
|
||||||
|
backend: 1.9.698
|
||||||
|
commit: ''
|
||||||
|
content: unknown
|
||||||
|
content_pack_name: unknown
|
||||||
|
format: '2'
|
||||||
|
frontend: 1.9.698
|
||||||
|
packs_version_avr8: 1.0.1463
|
||||||
|
packs_version_qtouch: unknown
|
||||||
|
packs_version_sam: 1.0.1726
|
||||||
|
version_backend: 1.9.698
|
||||||
|
version_frontend: ''
|
||||||
|
board:
|
||||||
|
identifier: CustomBoard
|
||||||
|
device: SAMD09C13A-SSU
|
||||||
|
details: null
|
||||||
|
application: null
|
||||||
|
middlewares: {}
|
||||||
|
drivers:
|
||||||
|
ADC_0:
|
||||||
|
user_label: ADC_0
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::ADC::driver_config_definition::ADC::HAL:Driver:ADC.Sync
|
||||||
|
functionality: ADC
|
||||||
|
api: HAL:Driver:ADC_Sync
|
||||||
|
configuration:
|
||||||
|
adc_advanced_settings: false
|
||||||
|
adc_arch_adjres: 0
|
||||||
|
adc_arch_corren: false
|
||||||
|
adc_arch_dbgrun: false
|
||||||
|
adc_arch_event_settings: false
|
||||||
|
adc_arch_gain: 1x
|
||||||
|
adc_arch_gaincorr: 0
|
||||||
|
adc_arch_inputoffset: 0
|
||||||
|
adc_arch_inputscan: 0
|
||||||
|
adc_arch_leftadj: false
|
||||||
|
adc_arch_offsetcorr: 0
|
||||||
|
adc_arch_refcomp: false
|
||||||
|
adc_arch_resrdyeo: false
|
||||||
|
adc_arch_runstdby: false
|
||||||
|
adc_arch_samplen: 0
|
||||||
|
adc_arch_samplenum: 1 sample
|
||||||
|
adc_arch_startei: false
|
||||||
|
adc_arch_syncei: false
|
||||||
|
adc_arch_winlt: 0
|
||||||
|
adc_arch_winmode: No window mode
|
||||||
|
adc_arch_winmoneo: false
|
||||||
|
adc_arch_winut: 0
|
||||||
|
adc_differential_mode: false
|
||||||
|
adc_freerunning_mode: false
|
||||||
|
adc_pinmux_negative: ADC AIN0 pin
|
||||||
|
adc_pinmux_positive: ADC AIN0 pin
|
||||||
|
adc_prescaler: Peripheral clock divided by 4
|
||||||
|
adc_reference: 1/2 VDDANA (only for VDDANA > 2.0V)
|
||||||
|
adc_resolution: 12-bit
|
||||||
|
optional_signals:
|
||||||
|
- identifier: ADC_0:AIN/2
|
||||||
|
pad: PA04
|
||||||
|
mode: Enabled
|
||||||
|
configuration: null
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::optional_signal_definition::ADC.AIN.2
|
||||||
|
name: ADC/AIN/2
|
||||||
|
label: AIN/2
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group:
|
||||||
|
nodes:
|
||||||
|
- name: ADC
|
||||||
|
input: Generic clock generator 0
|
||||||
|
external: false
|
||||||
|
external_frequency: 0
|
||||||
|
configuration:
|
||||||
|
adc_gclk_selection: Generic clock generator 0
|
||||||
|
EXTERNAL_IRQ_0:
|
||||||
|
user_label: EXTERNAL_IRQ_0
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ
|
||||||
|
functionality: External_IRQ
|
||||||
|
api: HAL:Driver:Ext_IRQ
|
||||||
|
configuration:
|
||||||
|
eic_arch_enable_irq_setting0: false
|
||||||
|
eic_arch_enable_irq_setting1: false
|
||||||
|
eic_arch_enable_irq_setting2: false
|
||||||
|
eic_arch_enable_irq_setting3: false
|
||||||
|
eic_arch_enable_irq_setting4: false
|
||||||
|
eic_arch_enable_irq_setting5: false
|
||||||
|
eic_arch_enable_irq_setting6: false
|
||||||
|
eic_arch_enable_irq_setting7: false
|
||||||
|
eic_arch_extinteo0: false
|
||||||
|
eic_arch_extinteo1: false
|
||||||
|
eic_arch_extinteo2: false
|
||||||
|
eic_arch_extinteo3: false
|
||||||
|
eic_arch_extinteo4: false
|
||||||
|
eic_arch_extinteo5: false
|
||||||
|
eic_arch_extinteo6: false
|
||||||
|
eic_arch_extinteo7: false
|
||||||
|
eic_arch_filten0: false
|
||||||
|
eic_arch_filten1: false
|
||||||
|
eic_arch_filten2: false
|
||||||
|
eic_arch_filten3: false
|
||||||
|
eic_arch_filten4: false
|
||||||
|
eic_arch_filten5: false
|
||||||
|
eic_arch_filten6: false
|
||||||
|
eic_arch_filten7: false
|
||||||
|
eic_arch_nmifilten: false
|
||||||
|
eic_arch_nmisense: No detection
|
||||||
|
eic_arch_sense0: No detection
|
||||||
|
eic_arch_sense1: No detection
|
||||||
|
eic_arch_sense2: No detection
|
||||||
|
eic_arch_sense3: No detection
|
||||||
|
eic_arch_sense4: No detection
|
||||||
|
eic_arch_sense5: No detection
|
||||||
|
eic_arch_sense6: No detection
|
||||||
|
eic_arch_sense7: No detection
|
||||||
|
eic_arch_wakeupen0: false
|
||||||
|
eic_arch_wakeupen1: false
|
||||||
|
eic_arch_wakeupen2: false
|
||||||
|
eic_arch_wakeupen3: false
|
||||||
|
eic_arch_wakeupen4: false
|
||||||
|
eic_arch_wakeupen5: false
|
||||||
|
eic_arch_wakeupen6: false
|
||||||
|
eic_arch_wakeupen7: false
|
||||||
|
optional_signals:
|
||||||
|
- identifier: EXTERNAL_IRQ_0:EXTINT/1
|
||||||
|
pad: PA15
|
||||||
|
mode: Enabled
|
||||||
|
configuration: null
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::optional_signal_definition::EIC.EXTINT.1
|
||||||
|
name: EIC/EXTINT/1
|
||||||
|
label: EXTINT/1
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group:
|
||||||
|
nodes:
|
||||||
|
- name: EIC
|
||||||
|
input: Generic clock generator 0
|
||||||
|
external: false
|
||||||
|
external_frequency: 0
|
||||||
|
configuration:
|
||||||
|
eic_gclk_selection: Generic clock generator 0
|
||||||
|
GCLK:
|
||||||
|
user_label: GCLK
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
|
||||||
|
functionality: System
|
||||||
|
api: HAL:HPL:GCLK
|
||||||
|
configuration:
|
||||||
|
$input: 400000
|
||||||
|
$input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
RESERVED_InputFreq: 400000
|
||||||
|
RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
_$freq_output_Generic clock generator 0: 1000000
|
||||||
|
_$freq_output_Generic clock generator 1: 400000
|
||||||
|
_$freq_output_Generic clock generator 2: 400000
|
||||||
|
_$freq_output_Generic clock generator 3: 400000
|
||||||
|
_$freq_output_Generic clock generator 4: 400000
|
||||||
|
_$freq_output_Generic clock generator 5: 400000
|
||||||
|
enable_gclk_gen_0: true
|
||||||
|
enable_gclk_gen_0__externalclock: 1000000
|
||||||
|
enable_gclk_gen_1: false
|
||||||
|
enable_gclk_gen_1__externalclock: 1000000
|
||||||
|
enable_gclk_gen_2: false
|
||||||
|
enable_gclk_gen_2__externalclock: 1000000
|
||||||
|
enable_gclk_gen_3: false
|
||||||
|
enable_gclk_gen_3__externalclock: 1000000
|
||||||
|
enable_gclk_gen_4: false
|
||||||
|
enable_gclk_gen_4__externalclock: 1000000
|
||||||
|
enable_gclk_gen_5: false
|
||||||
|
enable_gclk_gen_5__externalclock: 1000000
|
||||||
|
gclk_arch_gen_0_RUNSTDBY: false
|
||||||
|
gclk_arch_gen_0_enable: true
|
||||||
|
gclk_arch_gen_0_idc: false
|
||||||
|
gclk_arch_gen_0_oe: false
|
||||||
|
gclk_arch_gen_0_oov: false
|
||||||
|
gclk_arch_gen_1_RUNSTDBY: false
|
||||||
|
gclk_arch_gen_1_enable: false
|
||||||
|
gclk_arch_gen_1_idc: false
|
||||||
|
gclk_arch_gen_1_oe: false
|
||||||
|
gclk_arch_gen_1_oov: false
|
||||||
|
gclk_arch_gen_2_RUNSTDBY: false
|
||||||
|
gclk_arch_gen_2_enable: false
|
||||||
|
gclk_arch_gen_2_idc: false
|
||||||
|
gclk_arch_gen_2_oe: false
|
||||||
|
gclk_arch_gen_2_oov: false
|
||||||
|
gclk_arch_gen_3_RUNSTDBY: false
|
||||||
|
gclk_arch_gen_3_enable: false
|
||||||
|
gclk_arch_gen_3_idc: false
|
||||||
|
gclk_arch_gen_3_oe: false
|
||||||
|
gclk_arch_gen_3_oov: false
|
||||||
|
gclk_arch_gen_4_RUNSTDBY: false
|
||||||
|
gclk_arch_gen_4_enable: false
|
||||||
|
gclk_arch_gen_4_idc: false
|
||||||
|
gclk_arch_gen_4_oe: false
|
||||||
|
gclk_arch_gen_4_oov: false
|
||||||
|
gclk_arch_gen_5_RUNSTDBY: false
|
||||||
|
gclk_arch_gen_5_enable: false
|
||||||
|
gclk_arch_gen_5_idc: false
|
||||||
|
gclk_arch_gen_5_oe: false
|
||||||
|
gclk_arch_gen_5_oov: false
|
||||||
|
gclk_gen_0_div: 1
|
||||||
|
gclk_gen_0_div_sel: false
|
||||||
|
gclk_gen_0_oscillator: 8MHz Internal Oscillator (OSC8M)
|
||||||
|
gclk_gen_1_div: 1
|
||||||
|
gclk_gen_1_div_sel: false
|
||||||
|
gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
gclk_gen_2_div: 1
|
||||||
|
gclk_gen_2_div_sel: false
|
||||||
|
gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
gclk_gen_3_div: 1
|
||||||
|
gclk_gen_3_div_sel: false
|
||||||
|
gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
gclk_gen_4_div: 1
|
||||||
|
gclk_gen_4_div_sel: false
|
||||||
|
gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
gclk_gen_5_div: 1
|
||||||
|
gclk_gen_5_div_sel: false
|
||||||
|
gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
optional_signals: []
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group: null
|
||||||
|
PM:
|
||||||
|
user_label: PM
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::PM::driver_config_definition::PM::HAL:HPL:PM
|
||||||
|
functionality: System
|
||||||
|
api: HAL:HPL:PM
|
||||||
|
configuration:
|
||||||
|
$input: 1000000
|
||||||
|
$input_id: Generic clock generator 0
|
||||||
|
RESERVED_InputFreq: 1000000
|
||||||
|
RESERVED_InputFreq_id: Generic clock generator 0
|
||||||
|
_$freq_output_CPU: 1000000
|
||||||
|
apba_div: '1'
|
||||||
|
apbb_div: '1'
|
||||||
|
apbc_div: '1'
|
||||||
|
cpu_clock_source: Generic clock generator 0
|
||||||
|
cpu_div: '1'
|
||||||
|
enable_cpu_clock: true
|
||||||
|
nvm_wait_states: '0'
|
||||||
|
optional_signals: []
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group:
|
||||||
|
nodes:
|
||||||
|
- name: CPU
|
||||||
|
input: CPU
|
||||||
|
external: false
|
||||||
|
external_frequency: 0
|
||||||
|
configuration: {}
|
||||||
|
DELAY_0:
|
||||||
|
user_label: DELAY_0
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::SysTick::driver_config_definition::Delay::HAL:Driver:Delay
|
||||||
|
functionality: Delay
|
||||||
|
api: HAL:Driver:Delay
|
||||||
|
configuration:
|
||||||
|
systick_arch_tickint: false
|
||||||
|
optional_signals: []
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group: null
|
||||||
|
TIMER_0:
|
||||||
|
user_label: TIMER_0
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::RTC::driver_config_definition::Timer::HAL:Driver:Timer
|
||||||
|
functionality: Timer
|
||||||
|
api: HAL:Driver:Timer
|
||||||
|
configuration:
|
||||||
|
rtc_arch_comp_val: 1024
|
||||||
|
rtc_arch_init_reset: true
|
||||||
|
rtc_arch_prescaler: Peripheral clock divided by 1
|
||||||
|
rtc_cmpeo0: false
|
||||||
|
rtc_event_control: false
|
||||||
|
rtc_ovfeo: false
|
||||||
|
rtc_pereo0: false
|
||||||
|
rtc_pereo1: false
|
||||||
|
rtc_pereo2: false
|
||||||
|
rtc_pereo3: false
|
||||||
|
rtc_pereo4: false
|
||||||
|
rtc_pereo5: false
|
||||||
|
rtc_pereo6: false
|
||||||
|
rtc_pereo7: false
|
||||||
|
optional_signals: []
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group:
|
||||||
|
nodes:
|
||||||
|
- name: RTC
|
||||||
|
input: Generic clock generator 0
|
||||||
|
external: false
|
||||||
|
external_frequency: 0
|
||||||
|
configuration:
|
||||||
|
rtc_clk_selection: Generic clock generator 0
|
||||||
|
DMAC:
|
||||||
|
user_label: DMAC
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
|
||||||
|
functionality: System
|
||||||
|
api: HAL:HPL:DMAC
|
||||||
|
configuration:
|
||||||
|
dmac_beatsize_0: 8-bit bus transfer
|
||||||
|
dmac_beatsize_1: 8-bit bus transfer
|
||||||
|
dmac_beatsize_10: 8-bit bus transfer
|
||||||
|
dmac_beatsize_11: 8-bit bus transfer
|
||||||
|
dmac_beatsize_12: 8-bit bus transfer
|
||||||
|
dmac_beatsize_13: 8-bit bus transfer
|
||||||
|
dmac_beatsize_14: 8-bit bus transfer
|
||||||
|
dmac_beatsize_15: 8-bit bus transfer
|
||||||
|
dmac_beatsize_2: 8-bit bus transfer
|
||||||
|
dmac_beatsize_3: 8-bit bus transfer
|
||||||
|
dmac_beatsize_4: 8-bit bus transfer
|
||||||
|
dmac_beatsize_5: 8-bit bus transfer
|
||||||
|
dmac_beatsize_6: 8-bit bus transfer
|
||||||
|
dmac_beatsize_7: 8-bit bus transfer
|
||||||
|
dmac_beatsize_8: 8-bit bus transfer
|
||||||
|
dmac_beatsize_9: 8-bit bus transfer
|
||||||
|
dmac_blockact_0: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_1: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_10: Channel will be disabled if it is the last block transfer
|
||||||
|
in the transaction
|
||||||
|
dmac_blockact_11: Channel will be disabled if it is the last block transfer
|
||||||
|
in the transaction
|
||||||
|
dmac_blockact_12: Channel will be disabled if it is the last block transfer
|
||||||
|
in the transaction
|
||||||
|
dmac_blockact_13: Channel will be disabled if it is the last block transfer
|
||||||
|
in the transaction
|
||||||
|
dmac_blockact_14: Channel will be disabled if it is the last block transfer
|
||||||
|
in the transaction
|
||||||
|
dmac_blockact_15: Channel will be disabled if it is the last block transfer
|
||||||
|
in the transaction
|
||||||
|
dmac_blockact_2: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_3: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_4: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_5: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_6: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_7: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_8: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_blockact_9: Channel will be disabled if it is the last block transfer in
|
||||||
|
the transaction
|
||||||
|
dmac_channel_0_settings: false
|
||||||
|
dmac_channel_10_settings: false
|
||||||
|
dmac_channel_11_settings: false
|
||||||
|
dmac_channel_12_settings: false
|
||||||
|
dmac_channel_13_settings: false
|
||||||
|
dmac_channel_14_settings: false
|
||||||
|
dmac_channel_15_settings: false
|
||||||
|
dmac_channel_1_settings: false
|
||||||
|
dmac_channel_2_settings: false
|
||||||
|
dmac_channel_3_settings: false
|
||||||
|
dmac_channel_4_settings: false
|
||||||
|
dmac_channel_5_settings: false
|
||||||
|
dmac_channel_6_settings: false
|
||||||
|
dmac_channel_7_settings: false
|
||||||
|
dmac_channel_8_settings: false
|
||||||
|
dmac_channel_9_settings: false
|
||||||
|
dmac_dbgrun: false
|
||||||
|
dmac_dstinc_0: false
|
||||||
|
dmac_dstinc_1: false
|
||||||
|
dmac_dstinc_10: false
|
||||||
|
dmac_dstinc_11: false
|
||||||
|
dmac_dstinc_12: false
|
||||||
|
dmac_dstinc_13: false
|
||||||
|
dmac_dstinc_14: false
|
||||||
|
dmac_dstinc_15: false
|
||||||
|
dmac_dstinc_2: false
|
||||||
|
dmac_dstinc_3: false
|
||||||
|
dmac_dstinc_4: false
|
||||||
|
dmac_dstinc_5: false
|
||||||
|
dmac_dstinc_6: false
|
||||||
|
dmac_dstinc_7: false
|
||||||
|
dmac_dstinc_8: false
|
||||||
|
dmac_dstinc_9: false
|
||||||
|
dmac_enable: false
|
||||||
|
dmac_enable_0: false
|
||||||
|
dmac_enable_1: false
|
||||||
|
dmac_enable_10: false
|
||||||
|
dmac_enable_11: false
|
||||||
|
dmac_enable_12: false
|
||||||
|
dmac_enable_13: false
|
||||||
|
dmac_enable_14: false
|
||||||
|
dmac_enable_15: false
|
||||||
|
dmac_enable_2: false
|
||||||
|
dmac_enable_3: false
|
||||||
|
dmac_enable_4: false
|
||||||
|
dmac_enable_5: false
|
||||||
|
dmac_enable_6: false
|
||||||
|
dmac_enable_7: false
|
||||||
|
dmac_enable_8: false
|
||||||
|
dmac_enable_9: false
|
||||||
|
dmac_evact_0: No action
|
||||||
|
dmac_evact_1: No action
|
||||||
|
dmac_evact_10: No action
|
||||||
|
dmac_evact_11: No action
|
||||||
|
dmac_evact_12: No action
|
||||||
|
dmac_evact_13: No action
|
||||||
|
dmac_evact_14: No action
|
||||||
|
dmac_evact_15: No action
|
||||||
|
dmac_evact_2: No action
|
||||||
|
dmac_evact_3: No action
|
||||||
|
dmac_evact_4: No action
|
||||||
|
dmac_evact_5: No action
|
||||||
|
dmac_evact_6: No action
|
||||||
|
dmac_evact_7: No action
|
||||||
|
dmac_evact_8: No action
|
||||||
|
dmac_evact_9: No action
|
||||||
|
dmac_evie_0: false
|
||||||
|
dmac_evie_1: false
|
||||||
|
dmac_evie_10: false
|
||||||
|
dmac_evie_11: false
|
||||||
|
dmac_evie_12: false
|
||||||
|
dmac_evie_13: false
|
||||||
|
dmac_evie_14: false
|
||||||
|
dmac_evie_15: false
|
||||||
|
dmac_evie_2: false
|
||||||
|
dmac_evie_3: false
|
||||||
|
dmac_evie_4: false
|
||||||
|
dmac_evie_5: false
|
||||||
|
dmac_evie_6: false
|
||||||
|
dmac_evie_7: false
|
||||||
|
dmac_evie_8: false
|
||||||
|
dmac_evie_9: false
|
||||||
|
dmac_evoe_0: false
|
||||||
|
dmac_evoe_1: false
|
||||||
|
dmac_evoe_10: false
|
||||||
|
dmac_evoe_11: false
|
||||||
|
dmac_evoe_12: false
|
||||||
|
dmac_evoe_13: false
|
||||||
|
dmac_evoe_14: false
|
||||||
|
dmac_evoe_15: false
|
||||||
|
dmac_evoe_2: false
|
||||||
|
dmac_evoe_3: false
|
||||||
|
dmac_evoe_4: false
|
||||||
|
dmac_evoe_5: false
|
||||||
|
dmac_evoe_6: false
|
||||||
|
dmac_evoe_7: false
|
||||||
|
dmac_evoe_8: false
|
||||||
|
dmac_evoe_9: false
|
||||||
|
dmac_evosel_0: Event generation disabled
|
||||||
|
dmac_evosel_1: Event generation disabled
|
||||||
|
dmac_evosel_10: Event generation disabled
|
||||||
|
dmac_evosel_11: Event generation disabled
|
||||||
|
dmac_evosel_12: Event generation disabled
|
||||||
|
dmac_evosel_13: Event generation disabled
|
||||||
|
dmac_evosel_14: Event generation disabled
|
||||||
|
dmac_evosel_15: Event generation disabled
|
||||||
|
dmac_evosel_2: Event generation disabled
|
||||||
|
dmac_evosel_3: Event generation disabled
|
||||||
|
dmac_evosel_4: Event generation disabled
|
||||||
|
dmac_evosel_5: Event generation disabled
|
||||||
|
dmac_evosel_6: Event generation disabled
|
||||||
|
dmac_evosel_7: Event generation disabled
|
||||||
|
dmac_evosel_8: Event generation disabled
|
||||||
|
dmac_evosel_9: Event generation disabled
|
||||||
|
dmac_lvl_0: Channel priority 0
|
||||||
|
dmac_lvl_1: Channel priority 0
|
||||||
|
dmac_lvl_10: Channel priority 0
|
||||||
|
dmac_lvl_11: Channel priority 0
|
||||||
|
dmac_lvl_12: Channel priority 0
|
||||||
|
dmac_lvl_13: Channel priority 0
|
||||||
|
dmac_lvl_14: Channel priority 0
|
||||||
|
dmac_lvl_15: Channel priority 0
|
||||||
|
dmac_lvl_2: Channel priority 0
|
||||||
|
dmac_lvl_3: Channel priority 0
|
||||||
|
dmac_lvl_4: Channel priority 0
|
||||||
|
dmac_lvl_5: Channel priority 0
|
||||||
|
dmac_lvl_6: Channel priority 0
|
||||||
|
dmac_lvl_7: Channel priority 0
|
||||||
|
dmac_lvl_8: Channel priority 0
|
||||||
|
dmac_lvl_9: Channel priority 0
|
||||||
|
dmac_lvlen0: false
|
||||||
|
dmac_lvlen1: false
|
||||||
|
dmac_lvlen2: false
|
||||||
|
dmac_lvlen3: false
|
||||||
|
dmac_lvlpri0: 0
|
||||||
|
dmac_lvlpri1: 0
|
||||||
|
dmac_lvlpri2: 0
|
||||||
|
dmac_lvlpri3: 0
|
||||||
|
dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
|
||||||
|
dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
|
||||||
|
dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
|
||||||
|
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
|
||||||
|
dmac_srcinc_0: false
|
||||||
|
dmac_srcinc_1: false
|
||||||
|
dmac_srcinc_10: false
|
||||||
|
dmac_srcinc_11: false
|
||||||
|
dmac_srcinc_12: false
|
||||||
|
dmac_srcinc_13: false
|
||||||
|
dmac_srcinc_14: false
|
||||||
|
dmac_srcinc_15: false
|
||||||
|
dmac_srcinc_2: false
|
||||||
|
dmac_srcinc_3: false
|
||||||
|
dmac_srcinc_4: false
|
||||||
|
dmac_srcinc_5: false
|
||||||
|
dmac_srcinc_6: false
|
||||||
|
dmac_srcinc_7: false
|
||||||
|
dmac_srcinc_8: false
|
||||||
|
dmac_srcinc_9: false
|
||||||
|
dmac_stepsel_0: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_1: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_10: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_11: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_12: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_13: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_14: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_15: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_2: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_3: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_4: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_5: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_6: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_7: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_8: Step size settings apply to the destination address
|
||||||
|
dmac_stepsel_9: Step size settings apply to the destination address
|
||||||
|
dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||||
|
dmac_trifsrc_0: Only software/event triggers
|
||||||
|
dmac_trifsrc_1: Only software/event triggers
|
||||||
|
dmac_trifsrc_10: Only software/event triggers
|
||||||
|
dmac_trifsrc_11: Only software/event triggers
|
||||||
|
dmac_trifsrc_12: Only software/event triggers
|
||||||
|
dmac_trifsrc_13: Only software/event triggers
|
||||||
|
dmac_trifsrc_14: Only software/event triggers
|
||||||
|
dmac_trifsrc_15: Only software/event triggers
|
||||||
|
dmac_trifsrc_2: Only software/event triggers
|
||||||
|
dmac_trifsrc_3: Only software/event triggers
|
||||||
|
dmac_trifsrc_4: Only software/event triggers
|
||||||
|
dmac_trifsrc_5: Only software/event triggers
|
||||||
|
dmac_trifsrc_6: Only software/event triggers
|
||||||
|
dmac_trifsrc_7: Only software/event triggers
|
||||||
|
dmac_trifsrc_8: Only software/event triggers
|
||||||
|
dmac_trifsrc_9: Only software/event triggers
|
||||||
|
dmac_trigact_0: One trigger required for each block transfer
|
||||||
|
dmac_trigact_1: One trigger required for each block transfer
|
||||||
|
dmac_trigact_10: One trigger required for each block transfer
|
||||||
|
dmac_trigact_11: One trigger required for each block transfer
|
||||||
|
dmac_trigact_12: One trigger required for each block transfer
|
||||||
|
dmac_trigact_13: One trigger required for each block transfer
|
||||||
|
dmac_trigact_14: One trigger required for each block transfer
|
||||||
|
dmac_trigact_15: One trigger required for each block transfer
|
||||||
|
dmac_trigact_2: One trigger required for each block transfer
|
||||||
|
dmac_trigact_3: One trigger required for each block transfer
|
||||||
|
dmac_trigact_4: One trigger required for each block transfer
|
||||||
|
dmac_trigact_5: One trigger required for each block transfer
|
||||||
|
dmac_trigact_6: One trigger required for each block transfer
|
||||||
|
dmac_trigact_7: One trigger required for each block transfer
|
||||||
|
dmac_trigact_8: One trigger required for each block transfer
|
||||||
|
dmac_trigact_9: One trigger required for each block transfer
|
||||||
|
optional_signals: []
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group: null
|
||||||
|
SYSCTRL:
|
||||||
|
user_label: SYSCTRL
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::SYSCTRL::driver_config_definition::SYSCTRL::HAL:HPL:SYSCTRL
|
||||||
|
functionality: System
|
||||||
|
api: HAL:HPL:SYSCTRL
|
||||||
|
configuration:
|
||||||
|
$input: 400000
|
||||||
|
$input_id: Generic clock generator 3
|
||||||
|
RESERVED_InputFreq: 400000
|
||||||
|
RESERVED_InputFreq_id: Generic clock generator 3
|
||||||
|
_$freq_output_8MHz Internal Oscillator (OSC8M): 1000000
|
||||||
|
_$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
|
||||||
|
_$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
|
||||||
|
_$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 585925000
|
||||||
|
dfll48m_arch_bplckc: false
|
||||||
|
dfll48m_arch_calibration: false
|
||||||
|
dfll48m_arch_ccdis: false
|
||||||
|
dfll48m_arch_coarse: 31
|
||||||
|
dfll48m_arch_enable: false
|
||||||
|
dfll48m_arch_fine: 512
|
||||||
|
dfll48m_arch_llaw: false
|
||||||
|
dfll48m_arch_ondemand: true
|
||||||
|
dfll48m_arch_qldis: false
|
||||||
|
dfll48m_arch_runstdby: false
|
||||||
|
dfll48m_arch_stable: false
|
||||||
|
dfll48m_arch_waitlock: false
|
||||||
|
dfll48m_mode: Open Loop Mode
|
||||||
|
dfll48m_mul: 0
|
||||||
|
dfll48m_ref_clock: Generic clock generator 3
|
||||||
|
dfll_arch_cstep: 1
|
||||||
|
dfll_arch_fstep: 1
|
||||||
|
enable_dfll48m: false
|
||||||
|
enable_fdpll96m: false
|
||||||
|
enable_osc32k: false
|
||||||
|
enable_osc8m: true
|
||||||
|
enable_osculp32k: true
|
||||||
|
enable_xosc: false
|
||||||
|
enable_xosc32k: false
|
||||||
|
fdpll96m_arch_enable: false
|
||||||
|
fdpll96m_arch_lbypass: false
|
||||||
|
fdpll96m_arch_ondemand: true
|
||||||
|
fdpll96m_arch_runstdby: false
|
||||||
|
fdpll96m_clock_div: 0
|
||||||
|
fdpll96m_ldr: 1463
|
||||||
|
fdpll96m_ldrfrac: 13
|
||||||
|
fdpll96m_ref_clock: Generic clock generator 3
|
||||||
|
osc32k_arch_calib: 0
|
||||||
|
osc32k_arch_en1k: false
|
||||||
|
osc32k_arch_en32k: false
|
||||||
|
osc32k_arch_enable: false
|
||||||
|
osc32k_arch_ondemand: true
|
||||||
|
osc32k_arch_overwrite_calibration: false
|
||||||
|
osc32k_arch_runstdby: false
|
||||||
|
osc32k_arch_startup: 3 Clock Cycles (92us)
|
||||||
|
osc32k_arch_wrtlock: false
|
||||||
|
osc8m_arch_calib: 0
|
||||||
|
osc8m_arch_enable: true
|
||||||
|
osc8m_arch_ondemand: true
|
||||||
|
osc8m_arch_overwrite_calibration: false
|
||||||
|
osc8m_arch_runstdby: false
|
||||||
|
osc8m_presc: '8'
|
||||||
|
osculp32k_arch_calib: 0
|
||||||
|
osculp32k_arch_overwrite_calibration: false
|
||||||
|
osculp32k_arch_wrtlock: false
|
||||||
|
xosc32k_arch_aampen: false
|
||||||
|
xosc32k_arch_en1k: false
|
||||||
|
xosc32k_arch_en32k: false
|
||||||
|
xosc32k_arch_enable: false
|
||||||
|
xosc32k_arch_ondemand: true
|
||||||
|
xosc32k_arch_runstdby: false
|
||||||
|
xosc32k_arch_startup: 122 us
|
||||||
|
xosc32k_arch_wrtlock: false
|
||||||
|
xosc32k_arch_xtalen: false
|
||||||
|
xosc_arch_ampgc: false
|
||||||
|
xosc_arch_enable: false
|
||||||
|
xosc_arch_gain: 2Mhz
|
||||||
|
xosc_arch_ondemand: true
|
||||||
|
xosc_arch_runstdby: false
|
||||||
|
xosc_arch_startup: 31 us
|
||||||
|
xosc_arch_xtalen: false
|
||||||
|
xosc_frequency: 400000
|
||||||
|
optional_signals: []
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group: null
|
||||||
|
WDT_0:
|
||||||
|
user_label: WDT_0
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::WDT::driver_config_definition::WDT::HAL:Driver:WDT
|
||||||
|
functionality: WDT
|
||||||
|
api: HAL:Driver:WDT
|
||||||
|
configuration:
|
||||||
|
wdt_arch_per: 8 clock cycles
|
||||||
|
wdt_arch_window: 8 clock cycles
|
||||||
|
wdt_arch_window_en: false
|
||||||
|
optional_signals: []
|
||||||
|
variant: null
|
||||||
|
clocks:
|
||||||
|
domain_group:
|
||||||
|
nodes:
|
||||||
|
- name: WDT
|
||||||
|
input: Generic clock generator 0
|
||||||
|
external: false
|
||||||
|
external_frequency: 0
|
||||||
|
configuration:
|
||||||
|
wdt_gclk_selection: Generic clock generator 0
|
||||||
|
pads:
|
||||||
|
PIN_BUTTON:
|
||||||
|
name: PA15
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::pad::PA15
|
||||||
|
mode: Digital input
|
||||||
|
user_label: PIN_BUTTON
|
||||||
|
configuration: null
|
||||||
|
PIN_ADC:
|
||||||
|
name: PA04
|
||||||
|
definition: Atmel:SAMD09_Drivers:0.0.1::SAMD09C13A-SSU::pad::PA04
|
||||||
|
mode: Analog
|
||||||
|
user_label: PIN_ADC
|
||||||
|
configuration: null
|
||||||
|
toolchain_options: []
|
||||||
|
static_files: []
|
||||||
26
Firmware/atmel_start_pins.h
Normal file
26
Firmware/atmel_start_pins.h
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
/*
|
||||||
|
* Code generated from Atmel Start.
|
||||||
|
*
|
||||||
|
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||||
|
* Please copy examples or other code you want to keep to a separate file
|
||||||
|
* to avoid losing it when reconfiguring.
|
||||||
|
*/
|
||||||
|
#ifndef ATMEL_START_PINS_H_INCLUDED
|
||||||
|
#define ATMEL_START_PINS_H_INCLUDED
|
||||||
|
|
||||||
|
#include <hal_gpio.h>
|
||||||
|
|
||||||
|
// SAMD09 has 7 pin functions
|
||||||
|
|
||||||
|
#define GPIO_PIN_FUNCTION_A 0
|
||||||
|
#define GPIO_PIN_FUNCTION_B 1
|
||||||
|
#define GPIO_PIN_FUNCTION_C 2
|
||||||
|
#define GPIO_PIN_FUNCTION_D 3
|
||||||
|
#define GPIO_PIN_FUNCTION_E 4
|
||||||
|
#define GPIO_PIN_FUNCTION_G 5
|
||||||
|
#define GPIO_PIN_FUNCTION_H 6
|
||||||
|
|
||||||
|
#define PIN_ADC GPIO(GPIO_PORTA, 4)
|
||||||
|
#define PIN_BUTTON GPIO(GPIO_PORTA, 15)
|
||||||
|
|
||||||
|
#endif // ATMEL_START_PINS_H_INCLUDED
|
||||||
296
Firmware/config/hpl_adc_config.h
Normal file
296
Firmware/config/hpl_adc_config.h
Normal file
@ -0,0 +1,296 @@
|
|||||||
|
/* Auto-generated config file hpl_adc_config.h */
|
||||||
|
#ifndef HPL_ADC_CONFIG_H
|
||||||
|
#define HPL_ADC_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
#ifndef CONF_ADC_0_ENABLE
|
||||||
|
#define CONF_ADC_0_ENABLE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> Basic Configuration
|
||||||
|
|
||||||
|
// <o> Conversion resolution
|
||||||
|
// <0x0=>12-bit
|
||||||
|
// <0x1=>16-bit (averaging must be enabled)
|
||||||
|
// <0x2=>10-bit
|
||||||
|
// <0x3=>8-bit
|
||||||
|
// <i> Defines the bit resolution for the ADC sample values (RESSEL)
|
||||||
|
// <id> adc_resolution
|
||||||
|
#ifndef CONF_ADC_0_RESSEL
|
||||||
|
#define CONF_ADC_0_RESSEL 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Reference Selection
|
||||||
|
// <0x0=>1.0V voltage reference
|
||||||
|
// <0x1=>1/1.48 VDDANA
|
||||||
|
// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
|
||||||
|
// <0x3=>External reference A
|
||||||
|
// <0x4=>External reference B
|
||||||
|
// <i> Select the reference for the ADC (REFSEL)
|
||||||
|
// <id> adc_reference
|
||||||
|
#ifndef CONF_ADC_0_REFSEL
|
||||||
|
#define CONF_ADC_0_REFSEL 0x2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Prescaler configuration
|
||||||
|
// <0x0=>Peripheral clock divided by 4
|
||||||
|
// <0x1=>Peripheral clock divided by 8
|
||||||
|
// <0x2=>Peripheral clock divided by 16
|
||||||
|
// <0x3=>Peripheral clock divided by 32
|
||||||
|
// <0x4=>Peripheral clock divided by 64
|
||||||
|
// <0x5=>Peripheral clock divided by 128
|
||||||
|
// <0x6=>Peripheral clock divided by 256
|
||||||
|
// <0x7=>Peripheral clock divided by 512
|
||||||
|
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
|
||||||
|
// <id> adc_prescaler
|
||||||
|
#ifndef CONF_ADC_0_PRESCALER
|
||||||
|
#define CONF_ADC_0_PRESCALER 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Free Running Mode
|
||||||
|
// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
|
||||||
|
// <id> adc_freerunning_mode
|
||||||
|
#ifndef CONF_ADC_0_FREERUN
|
||||||
|
#define CONF_ADC_0_FREERUN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Differential Mode
|
||||||
|
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
|
||||||
|
// <id> adc_differential_mode
|
||||||
|
#ifndef CONF_ADC_0_DIFFMODE
|
||||||
|
#define CONF_ADC_0_DIFFMODE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Positive Mux Input Selection
|
||||||
|
// <0x00=>ADC AIN0 pin
|
||||||
|
// <0x01=>ADC AIN1 pin
|
||||||
|
// <0x02=>ADC AIN2 pin
|
||||||
|
// <0x03=>ADC AIN3 pin
|
||||||
|
// <0x04=>ADC AIN4 pin
|
||||||
|
// <0x05=>ADC AIN5 pin
|
||||||
|
// <0x06=>ADC AIN6 pin
|
||||||
|
// <0x07=>ADC AIN7 pin
|
||||||
|
// <0x08=>ADC AIN8 pin
|
||||||
|
// <0x09=>ADC AIN9 pin
|
||||||
|
// <0x0A=>ADC AIN10 pin
|
||||||
|
// <0x0B=>ADC AIN11 pin
|
||||||
|
// <0x0C=>ADC AIN12 pin
|
||||||
|
// <0x0D=>ADC AIN13 pin
|
||||||
|
// <0x0E=>ADC AIN14 pin
|
||||||
|
// <0x0F=>ADC AIN15 pin
|
||||||
|
// <0x10=>ADC AIN16 pin
|
||||||
|
// <0x11=>ADC AIN17 pin
|
||||||
|
// <0x12=>ADC AIN18 pin
|
||||||
|
// <0x13=>ADC AIN19 pin
|
||||||
|
// <0x18=>Temperature reference
|
||||||
|
// <0x19=>Bandgap voltage
|
||||||
|
// <0x1A=>1/4 scaled core supply
|
||||||
|
// <0x1B=>1/4 scaled I/O supply
|
||||||
|
// <0x1C=>DAC output
|
||||||
|
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
|
||||||
|
// <id> adc_pinmux_positive
|
||||||
|
#ifndef CONF_ADC_0_MUXPOS
|
||||||
|
#define CONF_ADC_0_MUXPOS 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Negative Mux Input Selection
|
||||||
|
// <0x00=>ADC AIN0 pin
|
||||||
|
// <0x01=>ADC AIN1 pin
|
||||||
|
// <0x02=>ADC AIN2 pin
|
||||||
|
// <0x03=>ADC AIN3 pin
|
||||||
|
// <0x04=>ADC AIN4 pin
|
||||||
|
// <0x05=>ADC AIN5 pin
|
||||||
|
// <0x06=>ADC AIN6 pin
|
||||||
|
// <0x07=>ADC AIN7 pin
|
||||||
|
// <0x18=>Internal ground
|
||||||
|
// <0x19=>I/O ground
|
||||||
|
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
|
||||||
|
// <id> adc_pinmux_negative
|
||||||
|
#ifndef CONF_ADC_0_MUXNEG
|
||||||
|
#define CONF_ADC_0_MUXNEG 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <e> Advanced Configuration
|
||||||
|
// <id> adc_advanced_settings
|
||||||
|
#ifndef CONF_ADC_0_ADVANCED_CONFIG
|
||||||
|
#define CONF_ADC_0_ADVANCED_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Run in standby
|
||||||
|
// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
|
||||||
|
// <id> adc_arch_runstdby
|
||||||
|
#ifndef CONF_ADC_0_RUNSTDBY
|
||||||
|
#define CONF_ADC_0_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q>Debug Run
|
||||||
|
// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
|
||||||
|
// <id> adc_arch_dbgrun
|
||||||
|
#ifndef CONF_ADC_0_DBGRUN
|
||||||
|
#define CONF_ADC_0_DBGRUN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Left-Adjusted Result
|
||||||
|
// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
|
||||||
|
// <id> adc_arch_leftadj
|
||||||
|
#ifndef CONF_ADC_0_LEFTADJ
|
||||||
|
#define CONF_ADC_0_LEFTADJ 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Reference Buffer Offset Compensation Enable
|
||||||
|
// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
|
||||||
|
// <id> adc_arch_refcomp
|
||||||
|
#ifndef CONF_ADC_0_REFCOMP
|
||||||
|
#define CONF_ADC_0_REFCOMP 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Digital Correction Logic Enabled
|
||||||
|
// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
|
||||||
|
// <id> adc_arch_corren
|
||||||
|
#ifndef CONF_ADC_0_CORREN
|
||||||
|
#define CONF_ADC_0_CORREN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Offset Correction Value <0-4095>
|
||||||
|
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
|
||||||
|
// <id> adc_arch_offsetcorr
|
||||||
|
#ifndef CONF_ADC_0_OFFSETCORR
|
||||||
|
#define CONF_ADC_0_OFFSETCORR 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Gain Correction Value <0-4095>
|
||||||
|
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
|
||||||
|
// <id> adc_arch_gaincorr
|
||||||
|
#ifndef CONF_ADC_0_GAINCORR
|
||||||
|
#define CONF_ADC_0_GAINCORR 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Gain Factor Selection
|
||||||
|
// <0x0=>1x
|
||||||
|
// <0x1=>2x
|
||||||
|
// <0x2=>4x
|
||||||
|
// <0x3=>8x
|
||||||
|
// <0x4=>16x
|
||||||
|
// <0xF=>1/2x
|
||||||
|
// <i> These bits set the gain factor of the ADC gain stage. (GAIN)
|
||||||
|
// <id> adc_arch_gain
|
||||||
|
#ifndef CONF_ADC_0_GAIN
|
||||||
|
#define CONF_ADC_0_GAIN 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Adjusting Result / Division Coefficient <0-7>
|
||||||
|
// <i> These bits define the division coefficient in 2n steps. (ADJRES)
|
||||||
|
// <id> adc_arch_adjres
|
||||||
|
#ifndef CONF_ADC_0_ADJRES
|
||||||
|
#define CONF_ADC_0_ADJRES 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o.0..10> Number of Samples to be Collected
|
||||||
|
// <0x0=>1 sample
|
||||||
|
// <0x1=>2 samples
|
||||||
|
// <0x2=>4 samples
|
||||||
|
// <0x3=>8 samples
|
||||||
|
// <0x4=>16 samples
|
||||||
|
// <0x5=>32 samples
|
||||||
|
// <0x6=>64 samples
|
||||||
|
// <0x7=>128 samples
|
||||||
|
// <0x8=>256 samples
|
||||||
|
// <0x9=>512 samples
|
||||||
|
// <0xA=>1024 samples
|
||||||
|
// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
|
||||||
|
// <id> adc_arch_samplenum
|
||||||
|
#ifndef CONF_ADC_0_SAMPLENUM
|
||||||
|
#define CONF_ADC_0_SAMPLENUM 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Sampling Time Length <0-63>
|
||||||
|
// <i> These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
|
||||||
|
// <id> adc_arch_samplen
|
||||||
|
#ifndef CONF_ADC_0_SAMPLEN
|
||||||
|
#define CONF_ADC_0_SAMPLEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Window Monitor Mode
|
||||||
|
// <0x0=>No window mode
|
||||||
|
// <0x1=>Mode 1: RESULT above lower threshold
|
||||||
|
// <0x2=>Mode 2: RESULT beneath upper threshold
|
||||||
|
// <0x3=>Mode 3: RESULT inside lower and upper threshold
|
||||||
|
// <0x4=>Mode 4: RESULT outside lower and upper threshold
|
||||||
|
// <i> These bits enable and define the window monitor mode. (WINMODE)
|
||||||
|
// <id> adc_arch_winmode
|
||||||
|
#ifndef CONF_ADC_0_WINMODE
|
||||||
|
#define CONF_ADC_0_WINMODE 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Window Monitor Lower Threshold <0-65535>
|
||||||
|
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
|
||||||
|
// <id> adc_arch_winlt
|
||||||
|
#ifndef CONF_ADC_0_WINLT
|
||||||
|
#define CONF_ADC_0_WINLT 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Window Monitor Upper Threshold <0-65535>
|
||||||
|
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
|
||||||
|
// <id> adc_arch_winut
|
||||||
|
#ifndef CONF_ADC_0_WINUT
|
||||||
|
#define CONF_ADC_0_WINUT 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Number of Input Channels Included in Scan <0-15>
|
||||||
|
// <i>This register gives the number of input sources included in pin scan. The number of input sources included is INPUTSCAN + 1. 0 disables the input scan feature. (INPUTSCAN)
|
||||||
|
// <id> adc_arch_inputscan
|
||||||
|
#ifndef CONF_ADC_0_INPUTSCAN
|
||||||
|
#define CONF_ADC_0_INPUTSCAN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Positive Mux Setting Offset <0-15>
|
||||||
|
// <i>When inputscan is enabled this value define the pin offset, which means that the actual input pin sampled is the muxpos pin + input offset. (INPUTOFFSET)
|
||||||
|
// <id> adc_arch_inputoffset
|
||||||
|
#ifndef CONF_ADC_0_INPUTOFFSET
|
||||||
|
#define CONF_ADC_0_INPUTOFFSET 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> Event Control
|
||||||
|
// <id> adc_arch_event_settings
|
||||||
|
#ifndef CONF_ADC_0_EVENT_CONFIG
|
||||||
|
#define CONF_ADC_0_EVENT_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Window Monitor Event Out
|
||||||
|
// <i> Enables event output on window event (WINMONEO)
|
||||||
|
// <id> adc_arch_winmoneo
|
||||||
|
#ifndef CONF_ADC_0_WINMONEO
|
||||||
|
#define CONF_ADC_0_WINMONEO 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Result Ready Event Out
|
||||||
|
// <i> Enables event output on result ready event (RESRDEO)
|
||||||
|
// <id> adc_arch_resrdyeo
|
||||||
|
#ifndef CONF_ADC_0_RESRDYEO
|
||||||
|
#define CONF_ADC_0_RESRDYEO 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Trigger Synchronization On Event
|
||||||
|
// <i> Trigger a flush operation and a new conversion on event in (SYNCEI)
|
||||||
|
// <id> adc_arch_syncei
|
||||||
|
#ifndef CONF_ADC_0_SYNCEI
|
||||||
|
#define CONF_ADC_0_SYNCEI 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Trigger Conversion On Event
|
||||||
|
// <i> Trigger a conversion on event. (STARTEI)
|
||||||
|
// <id> adc_arch_startei
|
||||||
|
#ifndef CONF_ADC_0_STARTEI
|
||||||
|
#define CONF_ADC_0_STARTEI 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_ADC_CONFIG_H
|
||||||
2529
Firmware/config/hpl_dmac_config.h
Normal file
2529
Firmware/config/hpl_dmac_config.h
Normal file
File diff suppressed because it is too large
Load Diff
363
Firmware/config/hpl_eic_config.h
Normal file
363
Firmware/config/hpl_eic_config.h
Normal file
@ -0,0 +1,363 @@
|
|||||||
|
/* Auto-generated config file hpl_eic_config.h */
|
||||||
|
#ifndef HPL_EIC_CONFIG_H
|
||||||
|
#define HPL_EIC_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
// <h> Non-Maskable Interrupt Control
|
||||||
|
// <q> Non-Maskable Interrupt Filter Enable
|
||||||
|
// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
|
||||||
|
// <id> eic_arch_nmifilten
|
||||||
|
#ifndef CONF_EIC_NMIFILTEN
|
||||||
|
#define CONF_EIC_NMIFILTEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Non-Maskable Interrupt Sense
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines non-maskable interrupt sense
|
||||||
|
// <id> eic_arch_nmisense
|
||||||
|
#ifndef CONF_EIC_NMISENSE
|
||||||
|
#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <e> Interrupt 0 Settings
|
||||||
|
// <id> eic_arch_enable_irq_setting0
|
||||||
|
#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
|
||||||
|
#define CONF_EIC_ENABLE_IRQ_SETTING0 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 0 Event Output Enable
|
||||||
|
// <i> Indicates whether the external interrupt 0 event output is enabled or not
|
||||||
|
// <id> eic_arch_extinteo0
|
||||||
|
#ifndef CONF_EIC_EXTINTEO0
|
||||||
|
#define CONF_EIC_EXTINTEO0 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 0 Wake-up Enable
|
||||||
|
// <i> Indicates whether the external interrupt 0 wake-up is enabled or not
|
||||||
|
// <id> eic_arch_wakeupen0
|
||||||
|
#ifndef CONF_EIC_WAKEUPEN0
|
||||||
|
#define CONF_EIC_WAKEUPEN0 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 0 Filter Enable
|
||||||
|
// <i> Indicates whether the external interrupt 0 filter is enabled or not
|
||||||
|
// <id> eic_arch_filten0
|
||||||
|
#ifndef CONF_EIC_FILTEN0
|
||||||
|
#define CONF_EIC_FILTEN0 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Input 0 Sense Configuration
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines input sense trigger
|
||||||
|
// <id> eic_arch_sense0
|
||||||
|
#ifndef CONF_EIC_SENSE0
|
||||||
|
#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> Interrupt 1 Settings
|
||||||
|
// <id> eic_arch_enable_irq_setting1
|
||||||
|
#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
|
||||||
|
#define CONF_EIC_ENABLE_IRQ_SETTING1 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 1 Event Output Enable
|
||||||
|
// <i> Indicates whether the external interrupt 1 event output is enabled or not
|
||||||
|
// <id> eic_arch_extinteo1
|
||||||
|
#ifndef CONF_EIC_EXTINTEO1
|
||||||
|
#define CONF_EIC_EXTINTEO1 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 1 Wake-up Enable
|
||||||
|
// <i> Indicates whether the external interrupt 1 wake-up is enabled or not
|
||||||
|
// <id> eic_arch_wakeupen1
|
||||||
|
#ifndef CONF_EIC_WAKEUPEN1
|
||||||
|
#define CONF_EIC_WAKEUPEN1 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 1 Filter Enable
|
||||||
|
// <i> Indicates whether the external interrupt 1 filter is enabled or not
|
||||||
|
// <id> eic_arch_filten1
|
||||||
|
#ifndef CONF_EIC_FILTEN1
|
||||||
|
#define CONF_EIC_FILTEN1 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Input 1 Sense Configuration
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines input sense trigger
|
||||||
|
// <id> eic_arch_sense1
|
||||||
|
#ifndef CONF_EIC_SENSE1
|
||||||
|
#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> Interrupt 2 Settings
|
||||||
|
// <id> eic_arch_enable_irq_setting2
|
||||||
|
#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
|
||||||
|
#define CONF_EIC_ENABLE_IRQ_SETTING2 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 2 Event Output Enable
|
||||||
|
// <i> Indicates whether the external interrupt 2 event output is enabled or not
|
||||||
|
// <id> eic_arch_extinteo2
|
||||||
|
#ifndef CONF_EIC_EXTINTEO2
|
||||||
|
#define CONF_EIC_EXTINTEO2 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 2 Wake-up Enable
|
||||||
|
// <i> Indicates whether the external interrupt 2 wake-up is enabled or not
|
||||||
|
// <id> eic_arch_wakeupen2
|
||||||
|
#ifndef CONF_EIC_WAKEUPEN2
|
||||||
|
#define CONF_EIC_WAKEUPEN2 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 2 Filter Enable
|
||||||
|
// <i> Indicates whether the external interrupt 2 filter is enabled or not
|
||||||
|
// <id> eic_arch_filten2
|
||||||
|
#ifndef CONF_EIC_FILTEN2
|
||||||
|
#define CONF_EIC_FILTEN2 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Input 2 Sense Configuration
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines input sense trigger
|
||||||
|
// <id> eic_arch_sense2
|
||||||
|
#ifndef CONF_EIC_SENSE2
|
||||||
|
#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> Interrupt 3 Settings
|
||||||
|
// <id> eic_arch_enable_irq_setting3
|
||||||
|
#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
|
||||||
|
#define CONF_EIC_ENABLE_IRQ_SETTING3 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 3 Event Output Enable
|
||||||
|
// <i> Indicates whether the external interrupt 3 event output is enabled or not
|
||||||
|
// <id> eic_arch_extinteo3
|
||||||
|
#ifndef CONF_EIC_EXTINTEO3
|
||||||
|
#define CONF_EIC_EXTINTEO3 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 3 Wake-up Enable
|
||||||
|
// <i> Indicates whether the external interrupt 3 wake-up is enabled or not
|
||||||
|
// <id> eic_arch_wakeupen3
|
||||||
|
#ifndef CONF_EIC_WAKEUPEN3
|
||||||
|
#define CONF_EIC_WAKEUPEN3 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 3 Filter Enable
|
||||||
|
// <i> Indicates whether the external interrupt 3 filter is enabled or not
|
||||||
|
// <id> eic_arch_filten3
|
||||||
|
#ifndef CONF_EIC_FILTEN3
|
||||||
|
#define CONF_EIC_FILTEN3 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Input 3 Sense Configuration
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines input sense trigger
|
||||||
|
// <id> eic_arch_sense3
|
||||||
|
#ifndef CONF_EIC_SENSE3
|
||||||
|
#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> Interrupt 4 Settings
|
||||||
|
// <id> eic_arch_enable_irq_setting4
|
||||||
|
#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
|
||||||
|
#define CONF_EIC_ENABLE_IRQ_SETTING4 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 4 Event Output Enable
|
||||||
|
// <i> Indicates whether the external interrupt 4 event output is enabled or not
|
||||||
|
// <id> eic_arch_extinteo4
|
||||||
|
#ifndef CONF_EIC_EXTINTEO4
|
||||||
|
#define CONF_EIC_EXTINTEO4 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 4 Wake-up Enable
|
||||||
|
// <i> Indicates whether the external interrupt 4 wake-up is enabled or not
|
||||||
|
// <id> eic_arch_wakeupen4
|
||||||
|
#ifndef CONF_EIC_WAKEUPEN4
|
||||||
|
#define CONF_EIC_WAKEUPEN4 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 4 Filter Enable
|
||||||
|
// <i> Indicates whether the external interrupt 4 filter is enabled or not
|
||||||
|
// <id> eic_arch_filten4
|
||||||
|
#ifndef CONF_EIC_FILTEN4
|
||||||
|
#define CONF_EIC_FILTEN4 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Input 4 Sense Configuration
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines input sense trigger
|
||||||
|
// <id> eic_arch_sense4
|
||||||
|
#ifndef CONF_EIC_SENSE4
|
||||||
|
#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> Interrupt 5 Settings
|
||||||
|
// <id> eic_arch_enable_irq_setting5
|
||||||
|
#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
|
||||||
|
#define CONF_EIC_ENABLE_IRQ_SETTING5 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 5 Event Output Enable
|
||||||
|
// <i> Indicates whether the external interrupt 5 event output is enabled or not
|
||||||
|
// <id> eic_arch_extinteo5
|
||||||
|
#ifndef CONF_EIC_EXTINTEO5
|
||||||
|
#define CONF_EIC_EXTINTEO5 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 5 Wake-up Enable
|
||||||
|
// <i> Indicates whether the external interrupt 5 wake-up is enabled or not
|
||||||
|
// <id> eic_arch_wakeupen5
|
||||||
|
#ifndef CONF_EIC_WAKEUPEN5
|
||||||
|
#define CONF_EIC_WAKEUPEN5 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 5 Filter Enable
|
||||||
|
// <i> Indicates whether the external interrupt 5 filter is enabled or not
|
||||||
|
// <id> eic_arch_filten5
|
||||||
|
#ifndef CONF_EIC_FILTEN5
|
||||||
|
#define CONF_EIC_FILTEN5 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Input 5 Sense Configuration
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines input sense trigger
|
||||||
|
// <id> eic_arch_sense5
|
||||||
|
#ifndef CONF_EIC_SENSE5
|
||||||
|
#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> Interrupt 6 Settings
|
||||||
|
// <id> eic_arch_enable_irq_setting6
|
||||||
|
#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
|
||||||
|
#define CONF_EIC_ENABLE_IRQ_SETTING6 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 6 Event Output Enable
|
||||||
|
// <i> Indicates whether the external interrupt 6 event output is enabled or not
|
||||||
|
// <id> eic_arch_extinteo6
|
||||||
|
#ifndef CONF_EIC_EXTINTEO6
|
||||||
|
#define CONF_EIC_EXTINTEO6 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 6 Wake-up Enable
|
||||||
|
// <i> Indicates whether the external interrupt 6 wake-up is enabled or not
|
||||||
|
// <id> eic_arch_wakeupen6
|
||||||
|
#ifndef CONF_EIC_WAKEUPEN6
|
||||||
|
#define CONF_EIC_WAKEUPEN6 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 6 Filter Enable
|
||||||
|
// <i> Indicates whether the external interrupt 6 filter is enabled or not
|
||||||
|
// <id> eic_arch_filten6
|
||||||
|
#ifndef CONF_EIC_FILTEN6
|
||||||
|
#define CONF_EIC_FILTEN6 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Input 6 Sense Configuration
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines input sense trigger
|
||||||
|
// <id> eic_arch_sense6
|
||||||
|
#ifndef CONF_EIC_SENSE6
|
||||||
|
#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> Interrupt 7 Settings
|
||||||
|
// <id> eic_arch_enable_irq_setting7
|
||||||
|
#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
|
||||||
|
#define CONF_EIC_ENABLE_IRQ_SETTING7 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 7 Event Output Enable
|
||||||
|
// <i> Indicates whether the external interrupt 7 event output is enabled or not
|
||||||
|
// <id> eic_arch_extinteo7
|
||||||
|
#ifndef CONF_EIC_EXTINTEO7
|
||||||
|
#define CONF_EIC_EXTINTEO7 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 7 Wake-up Enable
|
||||||
|
// <i> Indicates whether the external interrupt 7 wake-up is enabled or not
|
||||||
|
// <id> eic_arch_wakeupen7
|
||||||
|
#ifndef CONF_EIC_WAKEUPEN7
|
||||||
|
#define CONF_EIC_WAKEUPEN7 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> External Interrupt 7 Filter Enable
|
||||||
|
// <i> Indicates whether the external interrupt 7 filter is enabled or not
|
||||||
|
// <id> eic_arch_filten7
|
||||||
|
#ifndef CONF_EIC_FILTEN7
|
||||||
|
#define CONF_EIC_FILTEN7 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Input 7 Sense Configuration
|
||||||
|
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||||
|
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||||
|
// <i> This defines input sense trigger
|
||||||
|
// <id> eic_arch_sense7
|
||||||
|
#ifndef CONF_EIC_SENSE7
|
||||||
|
#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||||
|
#endif
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
#ifndef CONFIG_EIC_EXTINT_MAP
|
||||||
|
#define CONFIG_EIC_EXTINT_MAP {1, PIN_PA15},
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_EIC_CONFIG_H
|
||||||
466
Firmware/config/hpl_gclk_config.h
Normal file
466
Firmware/config/hpl_gclk_config.h
Normal file
@ -0,0 +1,466 @@
|
|||||||
|
/* Auto-generated config file hpl_gclk_config.h */
|
||||||
|
#ifndef HPL_GCLK_CONFIG_H
|
||||||
|
#define HPL_GCLK_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
// <e> Generic clock generator 0 configuration
|
||||||
|
// <i> Indicates whether generic clock 0 configuration is enabled or not
|
||||||
|
// <id> enable_gclk_gen_0
|
||||||
|
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
|
||||||
|
#define CONF_GCLK_GENERATOR_0_CONFIG 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> Generic Clock Generator Control
|
||||||
|
// <q> Run in Standby
|
||||||
|
// <i> Indicates whether Run in Standby is enabled or not
|
||||||
|
// <id> gclk_arch_gen_0_RUNSTDBY
|
||||||
|
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
|
||||||
|
#define CONF_GCLK_GEN_0_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Divide Selection
|
||||||
|
// <i> Indicates whether Divide Selection is enabled or not
|
||||||
|
// <id> gclk_gen_0_div_sel
|
||||||
|
#ifndef CONF_GCLK_GEN_0_DIVSEL
|
||||||
|
#define CONF_GCLK_GEN_0_DIVSEL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Enable
|
||||||
|
// <i> Indicates whether Output Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_0_oe
|
||||||
|
#ifndef CONF_GCLK_GEN_0_OE
|
||||||
|
#define CONF_GCLK_GEN_0_OE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Off Value
|
||||||
|
// <i> Indicates whether Output Off Value is enabled or not
|
||||||
|
// <id> gclk_arch_gen_0_oov
|
||||||
|
#ifndef CONF_GCLK_GEN_0_OOV
|
||||||
|
#define CONF_GCLK_GEN_0_OOV 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Improve Duty Cycle
|
||||||
|
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||||
|
// <id> gclk_arch_gen_0_idc
|
||||||
|
#ifndef CONF_GCLK_GEN_0_IDC
|
||||||
|
#define CONF_GCLK_GEN_0_IDC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Generic Clock Generator Enable
|
||||||
|
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_0_enable
|
||||||
|
#ifndef CONF_GCLK_GEN_0_GENEN
|
||||||
|
#define CONF_GCLK_GEN_0_GENEN 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Generic clock generator 0 source
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||||
|
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
|
||||||
|
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||||
|
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||||
|
// <i> This defines the clock source for generic clock generator 0
|
||||||
|
// <id> gclk_gen_0_oscillator
|
||||||
|
#ifndef CONF_GCLK_GEN_0_SRC
|
||||||
|
#define CONF_GCLK_GEN_0_SRC GCLK_GENCTRL_SRC_OSC8M
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
//<h> Generic Clock Generator Division
|
||||||
|
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
|
||||||
|
// <i>
|
||||||
|
// <id> gclk_gen_0_div
|
||||||
|
#ifndef CONF_GCLK_GEN_0_DIV
|
||||||
|
#define CONF_GCLK_GEN_0_DIV 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>// <e> Generic clock generator 1 configuration
|
||||||
|
// <i> Indicates whether generic clock 1 configuration is enabled or not
|
||||||
|
// <id> enable_gclk_gen_1
|
||||||
|
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
|
||||||
|
#define CONF_GCLK_GENERATOR_1_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> Generic Clock Generator Control
|
||||||
|
// <q> Run in Standby
|
||||||
|
// <i> Indicates whether Run in Standby is enabled or not
|
||||||
|
// <id> gclk_arch_gen_1_RUNSTDBY
|
||||||
|
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
|
||||||
|
#define CONF_GCLK_GEN_1_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Divide Selection
|
||||||
|
// <i> Indicates whether Divide Selection is enabled or not
|
||||||
|
// <id> gclk_gen_1_div_sel
|
||||||
|
#ifndef CONF_GCLK_GEN_1_DIVSEL
|
||||||
|
#define CONF_GCLK_GEN_1_DIVSEL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Enable
|
||||||
|
// <i> Indicates whether Output Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_1_oe
|
||||||
|
#ifndef CONF_GCLK_GEN_1_OE
|
||||||
|
#define CONF_GCLK_GEN_1_OE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Off Value
|
||||||
|
// <i> Indicates whether Output Off Value is enabled or not
|
||||||
|
// <id> gclk_arch_gen_1_oov
|
||||||
|
#ifndef CONF_GCLK_GEN_1_OOV
|
||||||
|
#define CONF_GCLK_GEN_1_OOV 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Improve Duty Cycle
|
||||||
|
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||||
|
// <id> gclk_arch_gen_1_idc
|
||||||
|
#ifndef CONF_GCLK_GEN_1_IDC
|
||||||
|
#define CONF_GCLK_GEN_1_IDC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Generic Clock Generator Enable
|
||||||
|
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_1_enable
|
||||||
|
#ifndef CONF_GCLK_GEN_1_GENEN
|
||||||
|
#define CONF_GCLK_GEN_1_GENEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Generic clock generator 1 source
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||||
|
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
|
||||||
|
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||||
|
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||||
|
// <i> This defines the clock source for generic clock generator 1
|
||||||
|
// <id> gclk_gen_1_oscillator
|
||||||
|
#ifndef CONF_GCLK_GEN_1_SRC
|
||||||
|
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
//<h> Generic Clock Generator Division
|
||||||
|
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
|
||||||
|
// <i>
|
||||||
|
// <id> gclk_gen_1_div
|
||||||
|
#ifndef CONF_GCLK_GEN_1_DIV
|
||||||
|
#define CONF_GCLK_GEN_1_DIV 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>// <e> Generic clock generator 2 configuration
|
||||||
|
// <i> Indicates whether generic clock 2 configuration is enabled or not
|
||||||
|
// <id> enable_gclk_gen_2
|
||||||
|
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
|
||||||
|
#define CONF_GCLK_GENERATOR_2_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> Generic Clock Generator Control
|
||||||
|
// <q> Run in Standby
|
||||||
|
// <i> Indicates whether Run in Standby is enabled or not
|
||||||
|
// <id> gclk_arch_gen_2_RUNSTDBY
|
||||||
|
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
|
||||||
|
#define CONF_GCLK_GEN_2_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Divide Selection
|
||||||
|
// <i> Indicates whether Divide Selection is enabled or not
|
||||||
|
// <id> gclk_gen_2_div_sel
|
||||||
|
#ifndef CONF_GCLK_GEN_2_DIVSEL
|
||||||
|
#define CONF_GCLK_GEN_2_DIVSEL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Enable
|
||||||
|
// <i> Indicates whether Output Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_2_oe
|
||||||
|
#ifndef CONF_GCLK_GEN_2_OE
|
||||||
|
#define CONF_GCLK_GEN_2_OE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Off Value
|
||||||
|
// <i> Indicates whether Output Off Value is enabled or not
|
||||||
|
// <id> gclk_arch_gen_2_oov
|
||||||
|
#ifndef CONF_GCLK_GEN_2_OOV
|
||||||
|
#define CONF_GCLK_GEN_2_OOV 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Improve Duty Cycle
|
||||||
|
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||||
|
// <id> gclk_arch_gen_2_idc
|
||||||
|
#ifndef CONF_GCLK_GEN_2_IDC
|
||||||
|
#define CONF_GCLK_GEN_2_IDC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Generic Clock Generator Enable
|
||||||
|
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_2_enable
|
||||||
|
#ifndef CONF_GCLK_GEN_2_GENEN
|
||||||
|
#define CONF_GCLK_GEN_2_GENEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Generic clock generator 2 source
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||||
|
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
|
||||||
|
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||||
|
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||||
|
// <i> This defines the clock source for generic clock generator 2
|
||||||
|
// <id> gclk_gen_2_oscillator
|
||||||
|
#ifndef CONF_GCLK_GEN_2_SRC
|
||||||
|
#define CONF_GCLK_GEN_2_SRC GCLK_GENCTRL_SRC_XOSC
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
//<h> Generic Clock Generator Division
|
||||||
|
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
|
||||||
|
// <i>
|
||||||
|
// <id> gclk_gen_2_div
|
||||||
|
#ifndef CONF_GCLK_GEN_2_DIV
|
||||||
|
#define CONF_GCLK_GEN_2_DIV 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>// <e> Generic clock generator 3 configuration
|
||||||
|
// <i> Indicates whether generic clock 3 configuration is enabled or not
|
||||||
|
// <id> enable_gclk_gen_3
|
||||||
|
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
|
||||||
|
#define CONF_GCLK_GENERATOR_3_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> Generic Clock Generator Control
|
||||||
|
// <q> Run in Standby
|
||||||
|
// <i> Indicates whether Run in Standby is enabled or not
|
||||||
|
// <id> gclk_arch_gen_3_RUNSTDBY
|
||||||
|
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
|
||||||
|
#define CONF_GCLK_GEN_3_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Divide Selection
|
||||||
|
// <i> Indicates whether Divide Selection is enabled or not
|
||||||
|
// <id> gclk_gen_3_div_sel
|
||||||
|
#ifndef CONF_GCLK_GEN_3_DIVSEL
|
||||||
|
#define CONF_GCLK_GEN_3_DIVSEL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Enable
|
||||||
|
// <i> Indicates whether Output Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_3_oe
|
||||||
|
#ifndef CONF_GCLK_GEN_3_OE
|
||||||
|
#define CONF_GCLK_GEN_3_OE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Off Value
|
||||||
|
// <i> Indicates whether Output Off Value is enabled or not
|
||||||
|
// <id> gclk_arch_gen_3_oov
|
||||||
|
#ifndef CONF_GCLK_GEN_3_OOV
|
||||||
|
#define CONF_GCLK_GEN_3_OOV 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Improve Duty Cycle
|
||||||
|
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||||
|
// <id> gclk_arch_gen_3_idc
|
||||||
|
#ifndef CONF_GCLK_GEN_3_IDC
|
||||||
|
#define CONF_GCLK_GEN_3_IDC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Generic Clock Generator Enable
|
||||||
|
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_3_enable
|
||||||
|
#ifndef CONF_GCLK_GEN_3_GENEN
|
||||||
|
#define CONF_GCLK_GEN_3_GENEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Generic clock generator 3 source
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||||
|
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
|
||||||
|
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||||
|
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||||
|
// <i> This defines the clock source for generic clock generator 3
|
||||||
|
// <id> gclk_gen_3_oscillator
|
||||||
|
#ifndef CONF_GCLK_GEN_3_SRC
|
||||||
|
#define CONF_GCLK_GEN_3_SRC GCLK_GENCTRL_SRC_XOSC
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
//<h> Generic Clock Generator Division
|
||||||
|
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
|
||||||
|
// <i>
|
||||||
|
// <id> gclk_gen_3_div
|
||||||
|
#ifndef CONF_GCLK_GEN_3_DIV
|
||||||
|
#define CONF_GCLK_GEN_3_DIV 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>// <e> Generic clock generator 4 configuration
|
||||||
|
// <i> Indicates whether generic clock 4 configuration is enabled or not
|
||||||
|
// <id> enable_gclk_gen_4
|
||||||
|
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
|
||||||
|
#define CONF_GCLK_GENERATOR_4_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> Generic Clock Generator Control
|
||||||
|
// <q> Run in Standby
|
||||||
|
// <i> Indicates whether Run in Standby is enabled or not
|
||||||
|
// <id> gclk_arch_gen_4_RUNSTDBY
|
||||||
|
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
|
||||||
|
#define CONF_GCLK_GEN_4_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Divide Selection
|
||||||
|
// <i> Indicates whether Divide Selection is enabled or not
|
||||||
|
// <id> gclk_gen_4_div_sel
|
||||||
|
#ifndef CONF_GCLK_GEN_4_DIVSEL
|
||||||
|
#define CONF_GCLK_GEN_4_DIVSEL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Enable
|
||||||
|
// <i> Indicates whether Output Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_4_oe
|
||||||
|
#ifndef CONF_GCLK_GEN_4_OE
|
||||||
|
#define CONF_GCLK_GEN_4_OE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Off Value
|
||||||
|
// <i> Indicates whether Output Off Value is enabled or not
|
||||||
|
// <id> gclk_arch_gen_4_oov
|
||||||
|
#ifndef CONF_GCLK_GEN_4_OOV
|
||||||
|
#define CONF_GCLK_GEN_4_OOV 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Improve Duty Cycle
|
||||||
|
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||||
|
// <id> gclk_arch_gen_4_idc
|
||||||
|
#ifndef CONF_GCLK_GEN_4_IDC
|
||||||
|
#define CONF_GCLK_GEN_4_IDC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Generic Clock Generator Enable
|
||||||
|
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_4_enable
|
||||||
|
#ifndef CONF_GCLK_GEN_4_GENEN
|
||||||
|
#define CONF_GCLK_GEN_4_GENEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Generic clock generator 4 source
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||||
|
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
|
||||||
|
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||||
|
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||||
|
// <i> This defines the clock source for generic clock generator 4
|
||||||
|
// <id> gclk_gen_4_oscillator
|
||||||
|
#ifndef CONF_GCLK_GEN_4_SRC
|
||||||
|
#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_XOSC
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
//<h> Generic Clock Generator Division
|
||||||
|
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
|
||||||
|
// <i>
|
||||||
|
// <id> gclk_gen_4_div
|
||||||
|
#ifndef CONF_GCLK_GEN_4_DIV
|
||||||
|
#define CONF_GCLK_GEN_4_DIV 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>// <e> Generic clock generator 5 configuration
|
||||||
|
// <i> Indicates whether generic clock 5 configuration is enabled or not
|
||||||
|
// <id> enable_gclk_gen_5
|
||||||
|
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
|
||||||
|
#define CONF_GCLK_GENERATOR_5_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> Generic Clock Generator Control
|
||||||
|
// <q> Run in Standby
|
||||||
|
// <i> Indicates whether Run in Standby is enabled or not
|
||||||
|
// <id> gclk_arch_gen_5_RUNSTDBY
|
||||||
|
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
|
||||||
|
#define CONF_GCLK_GEN_5_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Divide Selection
|
||||||
|
// <i> Indicates whether Divide Selection is enabled or not
|
||||||
|
// <id> gclk_gen_5_div_sel
|
||||||
|
#ifndef CONF_GCLK_GEN_5_DIVSEL
|
||||||
|
#define CONF_GCLK_GEN_5_DIVSEL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Enable
|
||||||
|
// <i> Indicates whether Output Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_5_oe
|
||||||
|
#ifndef CONF_GCLK_GEN_5_OE
|
||||||
|
#define CONF_GCLK_GEN_5_OE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Output Off Value
|
||||||
|
// <i> Indicates whether Output Off Value is enabled or not
|
||||||
|
// <id> gclk_arch_gen_5_oov
|
||||||
|
#ifndef CONF_GCLK_GEN_5_OOV
|
||||||
|
#define CONF_GCLK_GEN_5_OOV 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Improve Duty Cycle
|
||||||
|
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||||
|
// <id> gclk_arch_gen_5_idc
|
||||||
|
#ifndef CONF_GCLK_GEN_5_IDC
|
||||||
|
#define CONF_GCLK_GEN_5_IDC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Generic Clock Generator Enable
|
||||||
|
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||||
|
// <id> gclk_arch_gen_5_enable
|
||||||
|
#ifndef CONF_GCLK_GEN_5_GENEN
|
||||||
|
#define CONF_GCLK_GEN_5_GENEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Generic clock generator 5 source
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||||
|
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||||
|
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
|
||||||
|
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||||
|
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||||
|
// <i> This defines the clock source for generic clock generator 5
|
||||||
|
// <id> gclk_gen_5_oscillator
|
||||||
|
#ifndef CONF_GCLK_GEN_5_SRC
|
||||||
|
#define CONF_GCLK_GEN_5_SRC GCLK_GENCTRL_SRC_XOSC
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
//<h> Generic Clock Generator Division
|
||||||
|
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
|
||||||
|
// <i>
|
||||||
|
// <id> gclk_gen_5_div
|
||||||
|
#ifndef CONF_GCLK_GEN_5_DIV
|
||||||
|
#define CONF_GCLK_GEN_5_DIV 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_GCLK_CONFIG_H
|
||||||
134
Firmware/config/hpl_pm_config.h
Normal file
134
Firmware/config/hpl_pm_config.h
Normal file
@ -0,0 +1,134 @@
|
|||||||
|
/* Auto-generated config file hpl_pm_config.h */
|
||||||
|
#ifndef HPL_PM_CONFIG_H
|
||||||
|
#define HPL_PM_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
#include <peripheral_clk_config.h>
|
||||||
|
|
||||||
|
// <e> System Configuration
|
||||||
|
// <i> Indicates whether configuration for system is enabled or not
|
||||||
|
// <id> enable_cpu_clock
|
||||||
|
#ifndef CONF_SYSTEM_CONFIG
|
||||||
|
#define CONF_SYSTEM_CONFIG 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> CPU Clock Settings
|
||||||
|
// <y> CPU Clock source
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||||
|
// <i> This defines the clock source for the CPU
|
||||||
|
// <id> cpu_clock_source
|
||||||
|
#ifndef CONF_CPU_SRC
|
||||||
|
#define CONF_CPU_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> CPU clock Prescalar
|
||||||
|
// <PM_CPUSEL_CPUDIV_DIV1_Val"> 1
|
||||||
|
// <PM_CPUSEL_CPUDIV_DIV2_Val"> 2
|
||||||
|
// <PM_CPUSEL_CPUDIV_DIV4_Val"> 4
|
||||||
|
// <PM_CPUSEL_CPUDIV_DIV8_Val"> 8
|
||||||
|
// <PM_CPUSEL_CPUDIV_DIV16_Val"> 16
|
||||||
|
// <PM_CPUSEL_CPUDIV_DIV32_Val"> 32
|
||||||
|
// <PM_CPUSEL_CPUDIV_DIV64_Val"> 64
|
||||||
|
// <PM_CPUSEL_CPUDIV_DIV128_Val"> 128
|
||||||
|
// <i> Prescalar for Main CPU clock
|
||||||
|
// <id> cpu_div
|
||||||
|
#ifndef CONF_CPU_DIV
|
||||||
|
#define CONF_CPU_DIV PM_CPUSEL_CPUDIV_DIV1_Val
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <h> NVM Settings
|
||||||
|
// <o> NVM Wait States
|
||||||
|
// <i> These bits select the number of wait states for a read operation.
|
||||||
|
// <0=> 0
|
||||||
|
// <1=> 1
|
||||||
|
// <2=> 2
|
||||||
|
// <3=> 3
|
||||||
|
// <4=> 4
|
||||||
|
// <5=> 5
|
||||||
|
// <6=> 6
|
||||||
|
// <7=> 7
|
||||||
|
// <8=> 8
|
||||||
|
// <9=> 9
|
||||||
|
// <10=> 10
|
||||||
|
// <11=> 11
|
||||||
|
// <12=> 12
|
||||||
|
// <13=> 13
|
||||||
|
// <14=> 14
|
||||||
|
// <15=> 15
|
||||||
|
// <id> nvm_wait_states
|
||||||
|
#ifndef CONF_NVM_WAIT_STATE
|
||||||
|
#define CONF_NVM_WAIT_STATE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <h> APBA Clock Select
|
||||||
|
// <y> APBA clock prescalar
|
||||||
|
// <PM_APBASEL_APBADIV_DIV1"> 1
|
||||||
|
// <PM_APBASEL_APBADIV_DIV2"> 2
|
||||||
|
// <PM_APBASEL_APBADIV_DIV4"> 4
|
||||||
|
// <PM_APBASEL_APBADIV_DIV8"> 8
|
||||||
|
// <PM_APBASEL_APBADIV_DIV16"> 16
|
||||||
|
// <PM_APBASEL_APBADIV_DIV32"> 32
|
||||||
|
// <PM_APBASEL_APBADIV_DIV64"> 64
|
||||||
|
// <PM_APBASEL_APBADIV_DIV128"> 128
|
||||||
|
// <i> APBA clock prescalar
|
||||||
|
// <id> apba_div
|
||||||
|
#ifndef CONF_APBA_DIV
|
||||||
|
#define CONF_APBA_DIV PM_APBASEL_APBADIV_DIV1
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
#if CONF_APBA_DIV < CONF_CPU_DIV
|
||||||
|
#warning APBA DIV cannot less than CPU DIV
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> APBB Clock Select
|
||||||
|
// <y> APBB clock prescalar
|
||||||
|
// <PM_APBBSEL_APBBDIV_DIV1"> 1
|
||||||
|
// <PM_APBBSEL_APBBDIV_DIV2"> 2
|
||||||
|
// <PM_APBBSEL_APBBDIV_DIV4"> 4
|
||||||
|
// <PM_APBBSEL_APBBDIV_DIV8"> 8
|
||||||
|
// <PM_APBBSEL_APBBDIV_DIV16"> 16
|
||||||
|
// <PM_APBBSEL_APBBDIV_DIV32"> 32
|
||||||
|
// <PM_APBBSEL_APBBDIV_DIV64"> 64
|
||||||
|
// <PM_APBBSEL_APBBDIV_DIV128"> 128
|
||||||
|
// <i> APBB clock prescalar
|
||||||
|
// <id> apbb_div
|
||||||
|
#ifndef CONF_APBB_DIV
|
||||||
|
#define CONF_APBB_DIV PM_APBBSEL_APBBDIV_DIV1
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
#if CONF_APBB_DIV < CONF_CPU_DIV
|
||||||
|
#warning APBB DIV cannot less than CPU DIV
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> APBC Clock Select
|
||||||
|
// <y> APBC clock prescalar
|
||||||
|
// <PM_APBCSEL_APBCDIV_DIV1"> 1
|
||||||
|
// <PM_APBCSEL_APBCDIV_DIV2"> 2
|
||||||
|
// <PM_APBCSEL_APBCDIV_DIV4"> 4
|
||||||
|
// <PM_APBCSEL_APBCDIV_DIV8"> 8
|
||||||
|
// <PM_APBCSEL_APBCDIV_DIV16"> 16
|
||||||
|
// <PM_APBCSEL_APBCDIV_DIV32"> 32
|
||||||
|
// <PM_APBCSEL_APBCDIV_DIV64"> 64
|
||||||
|
// <PM_APBCSEL_APBCDIV_DIV128"> 128
|
||||||
|
// <i> APBC clock prescalar
|
||||||
|
// <id> apbc_div
|
||||||
|
#ifndef CONF_APBC_DIV
|
||||||
|
#define CONF_APBC_DIV PM_APBCSEL_APBCDIV_DIV1
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
#if CONF_APBC_DIV < CONF_CPU_DIV
|
||||||
|
#warning APBC DIV cannot less than CPU DIV
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_PM_CONFIG_H
|
||||||
125
Firmware/config/hpl_rtc_config.h
Normal file
125
Firmware/config/hpl_rtc_config.h
Normal file
@ -0,0 +1,125 @@
|
|||||||
|
/* Auto-generated config file hpl_rtc_config.h */
|
||||||
|
#ifndef HPL_RTC_CONFIG_H
|
||||||
|
#define HPL_RTC_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
// <h> Basic settings
|
||||||
|
|
||||||
|
#ifndef CONF_RTC_ENABLE
|
||||||
|
#define CONF_RTC_ENABLE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Force reset RTC on initialization
|
||||||
|
// <i> Force RTC to reset on initialization, else init is not going on if RTC is already enabled.
|
||||||
|
// <i> Note that the previous power down data in RTC is lost if it's enabled.
|
||||||
|
// <id> rtc_arch_init_reset
|
||||||
|
#ifndef CONF_RTC_INIT_RESET
|
||||||
|
#define CONF_RTC_INIT_RESET 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Prescaler configuration
|
||||||
|
// <0x0=>Peripheral clock divided by 1
|
||||||
|
// <0x1=>Peripheral clock divided by 2
|
||||||
|
// <0x2=>Peripheral clock divided by 4
|
||||||
|
// <0x3=>Peripheral clock divided by 8
|
||||||
|
// <0x4=>Peripheral clock divided by 16
|
||||||
|
// <0x5=>Peripheral clock divided by 32
|
||||||
|
// <0x6=>Peripheral clock divided by 64
|
||||||
|
// <0x7=>Peripheral clock divided by 128
|
||||||
|
// <0x8=>Peripheral clock divided by 256
|
||||||
|
// <0x9=>Peripheral clock divided by 512
|
||||||
|
// <0xA=>Peripheral clock divided by 1024
|
||||||
|
// <i> These bits define the RTC clock relative to the peripheral clock
|
||||||
|
// <id> rtc_arch_prescaler
|
||||||
|
#ifndef CONF_RTC_PRESCALER
|
||||||
|
#define CONF_RTC_PRESCALER 0x0
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Compare Value <1-4294967295>
|
||||||
|
// <i> These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value),
|
||||||
|
// <i> by default 1M clock input, 1 prescaler, 1024 compare value, the ticks period equals to 1ms.
|
||||||
|
// <id> rtc_arch_comp_val
|
||||||
|
|
||||||
|
#ifndef CONF_RTC_COMP_VAL
|
||||||
|
#define CONF_RTC_COMP_VAL 1024
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <e> Event control
|
||||||
|
// <id> rtc_event_control
|
||||||
|
#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
|
||||||
|
#define CONF_RTC_EVENT_CONTROL_ENABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Periodic Interval 0 Event Output
|
||||||
|
// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
|
||||||
|
// <id> rtc_pereo0
|
||||||
|
#ifndef CONF_RTC_PEREO0
|
||||||
|
#define CONF_RTC_PEREO0 0
|
||||||
|
#endif
|
||||||
|
// <q> Periodic Interval 1 Event Output
|
||||||
|
// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
|
||||||
|
// <id> rtc_pereo1
|
||||||
|
#ifndef CONF_RTC_PEREO1
|
||||||
|
#define CONF_RTC_PEREO1 0
|
||||||
|
#endif
|
||||||
|
// <q> Periodic Interval 2 Event Output
|
||||||
|
// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
|
||||||
|
// <id> rtc_pereo2
|
||||||
|
#ifndef CONF_RTC_PEREO2
|
||||||
|
#define CONF_RTC_PEREO2 0
|
||||||
|
#endif
|
||||||
|
// <q> Periodic Interval 3 Event Output
|
||||||
|
// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
|
||||||
|
// <id> rtc_pereo3
|
||||||
|
#ifndef CONF_RTC_PEREO3
|
||||||
|
#define CONF_RTC_PEREO3 0
|
||||||
|
#endif
|
||||||
|
// <q> Periodic Interval 4 Event Output
|
||||||
|
// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
|
||||||
|
// <id> rtc_pereo4
|
||||||
|
#ifndef CONF_RTC_PEREO4
|
||||||
|
#define CONF_RTC_PEREO4 0
|
||||||
|
#endif
|
||||||
|
// <q> Periodic Interval 5 Event Output
|
||||||
|
// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
|
||||||
|
// <id> rtc_pereo5
|
||||||
|
#ifndef CONF_RTC_PEREO5
|
||||||
|
#define CONF_RTC_PEREO5 0
|
||||||
|
#endif
|
||||||
|
// <q> Periodic Interval 6 Event Output
|
||||||
|
// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
|
||||||
|
// <id> rtc_pereo6
|
||||||
|
#ifndef CONF_RTC_PEREO6
|
||||||
|
#define CONF_RTC_PEREO6 0
|
||||||
|
#endif
|
||||||
|
// <q> Periodic Interval 7 Event Output
|
||||||
|
// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
|
||||||
|
// <id> rtc_pereo7
|
||||||
|
#ifndef CONF_RTC_PEREO7
|
||||||
|
#define CONF_RTC_PEREO7 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Compare 0 Event Output
|
||||||
|
// <i> This bit indicates whether Compare O event is enabled and will be generated
|
||||||
|
// <id> rtc_cmpeo0
|
||||||
|
#ifndef CONF_RTC_COMPE0
|
||||||
|
#define CONF_RTC_COMPE0 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Overflow Event Output
|
||||||
|
// <i> This bit indicates whether Overflow event is enabled and will be generated
|
||||||
|
// <id> rtc_ovfeo
|
||||||
|
#ifndef CONF_RTC_OVFEO
|
||||||
|
#define CONF_RTC_OVFEO 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_RTC_CONFIG_H
|
||||||
662
Firmware/config/hpl_sysctrl_config.h
Normal file
662
Firmware/config/hpl_sysctrl_config.h
Normal file
@ -0,0 +1,662 @@
|
|||||||
|
/* Auto-generated config file hpl_sysctrl_config.h */
|
||||||
|
#ifndef HPL_SYSCTRL_CONFIG_H
|
||||||
|
#define HPL_SYSCTRL_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
#define CONF_DFLL_OPEN_LOOP_MODE 0
|
||||||
|
#define CONF_DFLL_CLOSED_LOOP_MODE 1
|
||||||
|
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_31MCS 0
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_61MCS 1
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_122MCS 2
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_244MCS 3
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_488MCS 4
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_977MCS 5
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_1953MCS 6
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_3906MCS 7
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_7813MCS 8
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_15625MCS 9
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_31250MCS 10
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_62500MCS 11
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_125000MCS 12
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_250000MCS 13
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_500000MCS 14
|
||||||
|
#define CONF_XOSC_STARTUP_TIME_1000000MCS 15
|
||||||
|
|
||||||
|
#define CONF_OSC_STARTUP_TIME_92MCS 0
|
||||||
|
#define CONF_OSC_STARTUP_TIME_122MCS 1
|
||||||
|
#define CONF_OSC_STARTUP_TIME_183MCS 2
|
||||||
|
#define CONF_OSC_STARTUP_TIME_305MCS 3
|
||||||
|
#define CONF_OSC_STARTUP_TIME_549MCS 4
|
||||||
|
#define CONF_OSC_STARTUP_TIME_1038MCS 5
|
||||||
|
#define CONF_OSC_STARTUP_TIME_2014MCS 6
|
||||||
|
#define CONF_OSC_STARTUP_TIME_3967MCS 7
|
||||||
|
|
||||||
|
#define CONF_XOSC32K_STARTUP_TIME_122MCS 0
|
||||||
|
#define CONF_XOSC32K_STARTUP_TIME_1068MCS 1
|
||||||
|
#define CONF_XOSC32K_STARTUP_TIME_65592MCS 2
|
||||||
|
#define CONF_XOSC32K_STARTUP_TIME_125092MCS 3
|
||||||
|
#define CONF_XOSC32K_STARTUP_TIME_500092MCS 4
|
||||||
|
#define CONF_XOSC32K_STARTUP_TIME_1000092MCS 5
|
||||||
|
#define CONF_XOSC32K_STARTUP_TIME_2000092MCS 6
|
||||||
|
#define CONF_XOSC32K_STARTUP_TIME_4000092MCS 7
|
||||||
|
|
||||||
|
// <e> 8MHz Internal Oscillator Configuration
|
||||||
|
// <i> Indicates whether configuration for OSC8M is enabled or not
|
||||||
|
// <id> enable_osc8m
|
||||||
|
#ifndef CONF_OSC8M_CONFIG
|
||||||
|
#define CONF_OSC8M_CONFIG 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> 8MHz Internal Oscillator (OSC8M) Control
|
||||||
|
// <q> Internal 8M Oscillator Enable
|
||||||
|
// <i> Indicates whether Internal 8 Mhz Oscillator is enabled or not
|
||||||
|
// <id> osc8m_arch_enable
|
||||||
|
#ifndef CONF_OSC8M_ENABLE
|
||||||
|
#define CONF_OSC8M_ENABLE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> On Demand Control
|
||||||
|
// <i> Indicates whether On Demand Control is enabled or not.
|
||||||
|
// <i> If enabled, the oscillator will only be running when requested by a peripheral.
|
||||||
|
// <i> If disabled, the oscillator will always be running when enabled.
|
||||||
|
// <id> osc8m_arch_ondemand
|
||||||
|
#ifndef CONF_OSC8M_ONDEMAND
|
||||||
|
#define CONF_OSC8M_ONDEMAND 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Run In Standby
|
||||||
|
// <i> Run In standby Mode
|
||||||
|
// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
|
||||||
|
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
|
||||||
|
// <id> osc8m_arch_runstdby
|
||||||
|
#ifndef CONF_OSC8M_RUNSTDBY
|
||||||
|
#define CONF_OSC8M_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Prescaler
|
||||||
|
// <SYSCTRL_OSC8M_PRESC_0_Val"> 1
|
||||||
|
// <SYSCTRL_OSC8M_PRESC_1_Val"> 2
|
||||||
|
// <SYSCTRL_OSC8M_PRESC_2_Val"> 4
|
||||||
|
// <SYSCTRL_OSC8M_PRESC_3_Val"> 8
|
||||||
|
// <i> Prescaler for Internal 8Mhz OSC
|
||||||
|
// <i> Default: No Prescaling
|
||||||
|
// <id> osc8m_presc
|
||||||
|
#ifndef CONF_OSC8M_PRESC
|
||||||
|
#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Overwrite Default Osc Calibration
|
||||||
|
// <i> Overwrite Default Osc Calibration
|
||||||
|
// <id> osc8m_arch_overwrite_calibration
|
||||||
|
#ifndef CONF_OSC8M_OVERWRITE_CALIBRATION
|
||||||
|
#define CONF_OSC8M_OVERWRITE_CALIBRATION 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o>Osc Calibration Value <0-65535>
|
||||||
|
// <i> Set the Oscillator Calibration Value
|
||||||
|
// <i> Default: 1
|
||||||
|
// <id> osc8m_arch_calib
|
||||||
|
#ifndef CONF_OSC8M_CALIB
|
||||||
|
#define CONF_OSC8M_CALIB 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> 32kHz Internal Oscillator Configuration
|
||||||
|
// <i> Indicates whether configuration for OSC32K is enabled or not
|
||||||
|
// <id> enable_osc32k
|
||||||
|
#ifndef CONF_OSC32K_CONFIG
|
||||||
|
#define CONF_OSC32K_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> 32kHz Internal Oscillator (OSC32K) Control
|
||||||
|
// <q> Internal 32K Oscillator Enable
|
||||||
|
// <i> Indicates whether Internal 32K Oscillator is enabled or not
|
||||||
|
// <id> osc32k_arch_enable
|
||||||
|
#ifndef CONF_OSC32K_ENABLE
|
||||||
|
#define CONF_OSC32K_ENABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> On Demand Control
|
||||||
|
// <i> Enable On Demand
|
||||||
|
// <i> If this bit is 0: The oscillator is always on, if enabled.
|
||||||
|
// <i> If this bit is 1, the oscillator will only be running when requested by a peripheral.
|
||||||
|
// <id> osc32k_arch_ondemand
|
||||||
|
#ifndef CONF_OSC32K_ONDEMAND
|
||||||
|
#define CONF_OSC32K_ONDEMAND 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Run In Standby
|
||||||
|
// <i> Run In standby Mode
|
||||||
|
// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
|
||||||
|
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
|
||||||
|
// <id> osc32k_arch_runstdby
|
||||||
|
#ifndef CONF_OSC32K_RUNSTDBY
|
||||||
|
#define CONF_OSC32K_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Enable 32Khz Output
|
||||||
|
// <i> Enable 32 Khz Output
|
||||||
|
// <id> osc32k_arch_en32k
|
||||||
|
#ifndef CONF_OSC32K_EN32K
|
||||||
|
#define CONF_OSC32K_EN32K 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Enable 1K
|
||||||
|
// <i> Enable 1K
|
||||||
|
// <id> osc32k_arch_en1k
|
||||||
|
#ifndef CONF_OSC32K_EN1K
|
||||||
|
#define CONF_OSC32K_EN1K 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Write Lock
|
||||||
|
// <i> Write Lock
|
||||||
|
// <id> osc32k_arch_wrtlock
|
||||||
|
#ifndef CONF_OSC32K_WRTLOCK
|
||||||
|
#define CONF_OSC32K_WRTLOCK 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Start up time for the 32K Oscillator
|
||||||
|
// <CONF_OSC_STARTUP_TIME_92MCS"> 3 Clock Cycles (92us)
|
||||||
|
// <CONF_OSC_STARTUP_TIME_122MCS"> 4 Clock Cycles (122us)
|
||||||
|
// <CONF_OSC_STARTUP_TIME_183MCS"> 6 Clock Cycles (183us)
|
||||||
|
// <CONF_OSC_STARTUP_TIME_305MCS"> 10 Clock Cycles (305us)
|
||||||
|
// <CONF_OSC_STARTUP_TIME_549MCS"> 18 Clock Cycles (549us)
|
||||||
|
// <CONF_OSC_STARTUP_TIME_1038MCS"> 34 Clock Cycles (1038us)
|
||||||
|
// <CONF_OSC_STARTUP_TIME_2014MCS"> 66 Clock Cycles (2014us)
|
||||||
|
// <CONF_OSC_STARTUP_TIME_3967MCS"> 130 Clock Cycles (3967us)
|
||||||
|
// <i> Start Up Time for the 32K Oscillator
|
||||||
|
// <i> Default: 10 Clock Cycles (305us)
|
||||||
|
// <id> osc32k_arch_startup
|
||||||
|
#ifndef CONF_OSC32K_STARTUP
|
||||||
|
#define CONF_OSC32K_STARTUP CONF_OSC_STARTUP_TIME_92MCS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Overwrite Default Osc Calibration
|
||||||
|
// <i> Overwrite Default Osc Calibration
|
||||||
|
// <id> osc32k_arch_overwrite_calibration
|
||||||
|
#ifndef CONF_OSC32K_OVERWRITE_CALIBRATION
|
||||||
|
#define CONF_OSC32K_OVERWRITE_CALIBRATION 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o>Osc Calibration Value <0-65535>
|
||||||
|
// <i> Set the Oscillator Calibration Value
|
||||||
|
// <i> Default: 0
|
||||||
|
// <id> osc32k_arch_calib
|
||||||
|
#ifndef CONF_OSC32K_CALIB
|
||||||
|
#define CONF_OSC32K_CALIB 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> 32kHz External Crystal Oscillator Configuration
|
||||||
|
// <i> Indicates whether configuration for External 32K Osc is enabled or not
|
||||||
|
// <id> enable_xosc32k
|
||||||
|
#ifndef CONF_XOSC32K_CONFIG
|
||||||
|
#define CONF_XOSC32K_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> 32kHz External Crystal Oscillator (XOSC32K) Control
|
||||||
|
// <q> External 32K Oscillator Enable
|
||||||
|
// <i> Indicates whether External 32K Oscillator is enabled or not
|
||||||
|
// <id> xosc32k_arch_enable
|
||||||
|
#ifndef CONF_XOSC32K_ENABLE
|
||||||
|
#define CONF_XOSC32K_ENABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> On Demand
|
||||||
|
// <i> Enable On Demand.
|
||||||
|
// <i> If this bit is 0: The oscillator is always on, if enabled.
|
||||||
|
// <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
|
||||||
|
// <id> xosc32k_arch_ondemand
|
||||||
|
#ifndef CONF_XOSC32K_ONDEMAND
|
||||||
|
#define CONF_XOSC32K_ONDEMAND 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Run In Standby
|
||||||
|
// <i> Run In standby Mode
|
||||||
|
// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
|
||||||
|
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
|
||||||
|
// <id> xosc32k_arch_runstdby
|
||||||
|
#ifndef CONF_XOSC32K_RUNSTDBY
|
||||||
|
#define CONF_XOSC32K_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Enable 1K
|
||||||
|
// <i> Enable 1K
|
||||||
|
// <id> xosc32k_arch_en1k
|
||||||
|
#ifndef CONF_XOSC32K_EN1K
|
||||||
|
#define CONF_XOSC32K_EN1K 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Enable 32Khz Output
|
||||||
|
// <i> Enable 32 Khz Output
|
||||||
|
// <id> xosc32k_arch_en32k
|
||||||
|
#ifndef CONF_XOSC32K_EN32K
|
||||||
|
#define CONF_XOSC32K_EN32K 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Enable XTAL
|
||||||
|
// <i> Enable XTAL
|
||||||
|
// <id> xosc32k_arch_xtalen
|
||||||
|
#ifndef CONF_XOSC32K_XTALEN
|
||||||
|
#define CONF_XOSC32K_XTALEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Write Lock
|
||||||
|
// <i> Write Lock
|
||||||
|
// <id> xosc32k_arch_wrtlock
|
||||||
|
#ifndef CONF_XOSC32K_WRTLOCK
|
||||||
|
#define CONF_XOSC32K_WRTLOCK 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Automatic Amplitude Control Enable
|
||||||
|
// <i> Indicates whether Automatic Amplitude Control is Enabled or not
|
||||||
|
// <id> xosc32k_arch_aampen
|
||||||
|
#ifndef CONF_XOSC32K_AAMPEN
|
||||||
|
#define CONF_XOSC32K_AAMPEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Start up time for the 32K Oscillator
|
||||||
|
// <CONF_XOSC32K_STARTUP_TIME_122MCS"> 122 us
|
||||||
|
// <CONF_XOSC32K_STARTUP_TIME_1068MCS"> 1068 us
|
||||||
|
// <CONF_XOSC32K_STARTUP_TIME_65592MCS"> 62592 us
|
||||||
|
// <CONF_XOSC32K_STARTUP_TIME_125092MCS"> 1125092 us
|
||||||
|
// <CONF_XOSC32K_STARTUP_TIME_500092MCS"> 500092 us
|
||||||
|
// <CONF_XOSC32K_STARTUP_TIME_1000092MCS"> 1000092 us
|
||||||
|
// <CONF_XOSC32K_STARTUP_TIME_2000092MCS"> 2000092 us
|
||||||
|
// <CONF_XOSC32K_STARTUP_TIME_4000092MCS"> 4000092 us
|
||||||
|
// <i> Start Up Time for the 32K Oscillator
|
||||||
|
// <i> Default: 122 us
|
||||||
|
// <id> xosc32k_arch_startup
|
||||||
|
#ifndef CONF_XOSC32K_STARTUP
|
||||||
|
#define CONF_XOSC32K_STARTUP CONF_XOSC32K_STARTUP_TIME_122MCS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||||
|
// <i> Indicates whether configuration for External Multipurpose Osc is enabled or not
|
||||||
|
// <id> enable_xosc
|
||||||
|
#ifndef CONF_XOSC_CONFIG
|
||||||
|
#define CONF_XOSC_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Frequency <400000-32000000>
|
||||||
|
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||||
|
// <id> xosc_frequency
|
||||||
|
#ifndef CONF_XOSC_FREQUENCY
|
||||||
|
#define CONF_XOSC_FREQUENCY 400000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> External Multipurpose Crystal Oscillator (XOSC) Control
|
||||||
|
// <q> Enable
|
||||||
|
// <i> Indicates whether External Multipurpose Oscillator is enabled or not
|
||||||
|
// <id> xosc_arch_enable
|
||||||
|
#ifndef CONF_XOSC_ENABLE
|
||||||
|
#define CONF_XOSC_ENABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> On Demand
|
||||||
|
// <i> Enable On Demand
|
||||||
|
// <i> If this bit is 0: The oscillator is always on, if enabled.
|
||||||
|
// <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
|
||||||
|
// <id> xosc_arch_ondemand
|
||||||
|
#ifndef CONF_XOSC_ONDEMAND
|
||||||
|
#define CONF_XOSC_ONDEMAND 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Run In Standby
|
||||||
|
// <i> Run In standby Mode
|
||||||
|
// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
|
||||||
|
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
|
||||||
|
// <id> xosc_arch_runstdby
|
||||||
|
#ifndef CONF_XOSC_RUNSTDBY
|
||||||
|
#define CONF_XOSC_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Enable XTAL
|
||||||
|
// <i> Enable XTAL
|
||||||
|
// <id> xosc_arch_xtalen
|
||||||
|
#ifndef CONF_XOSC_XTALEN
|
||||||
|
#define CONF_XOSC_XTALEN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Automatic Amplitude Control Enable
|
||||||
|
// <i> Indicates whether Automatic Amplitude Control is Enabled or not
|
||||||
|
// <id> xosc_arch_ampgc
|
||||||
|
#ifndef CONF_XOSC_AMPGC
|
||||||
|
#define CONF_XOSC_AMPGC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Gain of the Oscillator
|
||||||
|
// <SYSCTRL_XOSC_GAIN_0_Val"> 2Mhz
|
||||||
|
// <SYSCTRL_XOSC_GAIN_1_Val"> 4Mhz
|
||||||
|
// <SYSCTRL_XOSC_GAIN_2_Val"> 8Mhz
|
||||||
|
// <SYSCTRL_XOSC_GAIN_3_Val"> 16Mhz
|
||||||
|
// <SYSCTRL_XOSC_GAIN_4_Val"> 30Mhz
|
||||||
|
// <i> Select the Gain of the oscillator
|
||||||
|
// <id> xosc_arch_gain
|
||||||
|
#ifndef CONF_XOSC_GAIN
|
||||||
|
#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Start up time for the External Oscillator
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_31MCS"> 31 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_61MCS"> 61 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_122MCS"> 122 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_244MCS"> 244 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_488MCS"> 488 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_977MCS"> 977 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_1953MCS"> 1953 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_3906MCS"> 3906 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_7813MCS"> 7813 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_15625MCS"> 15625 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_31250MCS"> 31250 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_62500MCS"> 62500 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_125000MCS"> 125000 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_250000MCS"> 250000 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_500000MCS"> 500000 us
|
||||||
|
// <CONF_XOSC_STARTUP_TIME_1000000MCS"> 1000000 us
|
||||||
|
// <i> Start Up Time for the External Oscillator
|
||||||
|
// <i> Default: 31 us
|
||||||
|
// <id> xosc_arch_startup
|
||||||
|
#ifndef CONF_XOSC_STARTUP
|
||||||
|
#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
|
||||||
|
// <i> Indicates whether configuration for OSCULP32K is enabled or not
|
||||||
|
// <id> enable_osculp32k
|
||||||
|
#ifndef CONF_OSCULP32K_CONFIG
|
||||||
|
#define CONF_OSCULP32K_CONFIG 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
|
||||||
|
// <q> Write Lock
|
||||||
|
// <i> Locks the OSCULP32K register for future writes to fix the OSCULP32K configuration
|
||||||
|
// <id> osculp32k_arch_wrtlock
|
||||||
|
#ifndef CONF_OSCULP32K_WRTLOCK
|
||||||
|
#define CONF_OSCULP32K_WRTLOCK 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Overwrite Default Osc Calibration
|
||||||
|
// <i> Overwrite Default Osc Calibration
|
||||||
|
// <id> osculp32k_arch_overwrite_calibration
|
||||||
|
#ifndef CONF_OSCULP32K_OVERWRITE_CALIBRATION
|
||||||
|
#define CONF_OSCULP32K_OVERWRITE_CALIBRATION 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o>Osc Calibration Value <0-255>
|
||||||
|
// <i> Set the Oscillator Calibration Value
|
||||||
|
// <i> Default: 0
|
||||||
|
// <id> osculp32k_arch_calib
|
||||||
|
#ifndef CONF_OSCULP32K_CALIB
|
||||||
|
#define CONF_OSCULP32K_CALIB 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> DFLL Configuration
|
||||||
|
// <i> Indicates whether configuration for DFLL is enabled or not
|
||||||
|
// <id> enable_dfll48m
|
||||||
|
#ifndef CONF_DFLL_CONFIG
|
||||||
|
#define CONF_DFLL_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Reference Clock Source
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||||
|
// <i> Select the clock source.
|
||||||
|
// <id> dfll48m_ref_clock
|
||||||
|
#ifndef CONF_DFLL_GCLK
|
||||||
|
#define CONF_DFLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> DFLL Control
|
||||||
|
// <q> DFLL Enable
|
||||||
|
// <i> Indicates whether DFLL is enabled or not
|
||||||
|
// <id> dfll48m_arch_enable
|
||||||
|
#ifndef CONF_DFLL_ENABLE
|
||||||
|
#define CONF_DFLL_ENABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Wait Lock
|
||||||
|
// <i> Indicates whether Wait Lock is Enables or not
|
||||||
|
// <id> dfll48m_arch_waitlock
|
||||||
|
#ifndef CONF_DFLL_WAITLOCK
|
||||||
|
#define CONF_DFLL_WAITLOCK 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Bypass Coarse Lock
|
||||||
|
// <i> Indicates whether Bypass coarse lock is enabled or not
|
||||||
|
// <id> dfll48m_arch_bplckc
|
||||||
|
#ifndef CONF_DFLL_BPLCKC
|
||||||
|
#define CONF_DFLL_BPLCKC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Quick Lock Disable
|
||||||
|
// <i> Quick Lock Disable
|
||||||
|
// <id> dfll48m_arch_qldis
|
||||||
|
#ifndef CONF_DFLL_QLDIS
|
||||||
|
#define CONF_DFLL_QLDIS 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Chill Cycle Disable
|
||||||
|
// <i> Chill Cycle Disable
|
||||||
|
// <id> dfll48m_arch_ccdis
|
||||||
|
#ifndef CONF_DFLL_CCDIS
|
||||||
|
#define CONF_DFLL_CCDIS 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> On Demand
|
||||||
|
// <i> Enable On Demand
|
||||||
|
// <i> If this bit is 0: The DFLL is always on, if enabled.
|
||||||
|
// <i> If this bit is 1: the DFLL will only be running when requested by a peripheral.
|
||||||
|
// <id> dfll48m_arch_ondemand
|
||||||
|
#ifndef CONF_DFLL_ONDEMAND
|
||||||
|
#define CONF_DFLL_ONDEMAND 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Run In Standby
|
||||||
|
// <i> Run In standby Mode
|
||||||
|
// <i> If this bit is 0: The DFLL is disabled in standby sleep mode.
|
||||||
|
// <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
|
||||||
|
// <id> dfll48m_arch_runstdby
|
||||||
|
#ifndef CONF_DFLL_RUNSTDBY
|
||||||
|
#define CONF_DFLL_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Lose Lock After Wake
|
||||||
|
// <i> Lose Lock After Wake
|
||||||
|
// <id> dfll48m_arch_llaw
|
||||||
|
#ifndef CONF_DFLL_LLAW
|
||||||
|
#define CONF_DFLL_LLAW 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Stable DFLL Frequency
|
||||||
|
// <i> Stable DFLL Frequency
|
||||||
|
// <i> If 0: FINE calibration tracks changes in output frequency.
|
||||||
|
// <i> If 1: FINE calibration register value will be fixed after a fine lock.
|
||||||
|
// <id> dfll48m_arch_stable
|
||||||
|
#ifndef CONF_DFLL_STABLE
|
||||||
|
#define CONF_DFLL_STABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Operating Mode Selection
|
||||||
|
// <CONF_DFLL_OPEN_LOOP_MODE"> Open Loop Mode
|
||||||
|
// <CONF_DFLL_CLOSED_LOOP_MODE"> Closed Loop Mode
|
||||||
|
// <i> Mode
|
||||||
|
// <id> dfll48m_mode
|
||||||
|
#ifndef CONF_DFLL_MODE
|
||||||
|
#define CONF_DFLL_MODE CONF_DFLL_OPEN_LOOP_MODE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Coarse Maximum Step <0x0-0x1F>
|
||||||
|
// <id> dfll_arch_cstep
|
||||||
|
#ifndef CONF_DFLL_CSTEP
|
||||||
|
#define CONF_DFLL_CSTEP 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Fine Maximum Step <0x0-0x3FF>
|
||||||
|
// <id> dfll_arch_fstep
|
||||||
|
#ifndef CONF_DFLL_FSTEP
|
||||||
|
#define CONF_DFLL_FSTEP 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o>DFLL Multiply Factor<0-65535>
|
||||||
|
// <i> Set the DFLL Multiply Factor
|
||||||
|
// <i> Default: 0
|
||||||
|
// <id> dfll48m_mul
|
||||||
|
#ifndef CONF_DFLL_MUL
|
||||||
|
#define CONF_DFLL_MUL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <e> DFLL Calibration Overwrite
|
||||||
|
// <i> Indicates whether Overwrite Calibration value of DFLL
|
||||||
|
// <id> dfll48m_arch_calibration
|
||||||
|
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
|
||||||
|
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Coarse Value <0x0-0x3F>
|
||||||
|
// <id> dfll48m_arch_coarse
|
||||||
|
#ifndef CONF_DFLL_COARSE
|
||||||
|
#define CONF_DFLL_COARSE (0x1f)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Fine Value <0x0-0x3FF>
|
||||||
|
// <id> dfll48m_arch_fine
|
||||||
|
#ifndef CONF_DFLL_FINE
|
||||||
|
#define CONF_DFLL_FINE (0x200)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CONF_DFLL_OVERWRITE_CALIBRATION == 0
|
||||||
|
#define CONF_DEFAULT_CORASE \
|
||||||
|
((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos)
|
||||||
|
|
||||||
|
#define CONF_DFLLVAL \
|
||||||
|
SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \
|
||||||
|
| SYSCTRL_DFLLVAL_FINE(512)
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
//</e>
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// <e> DPLL Configuration
|
||||||
|
// <i> Indicates whether configuration for DPLL is enabled or not
|
||||||
|
// <id> enable_fdpll96m
|
||||||
|
#ifndef CONF_DPLL_CONFIG
|
||||||
|
#define CONF_DPLL_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> Reference Clock Source
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||||
|
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||||
|
// <i> Select the clock source.
|
||||||
|
// <id> fdpll96m_ref_clock
|
||||||
|
#ifndef CONF_DPLL_GCLK
|
||||||
|
#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K)
|
||||||
|
#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val
|
||||||
|
#elif (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC)
|
||||||
|
#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val
|
||||||
|
#else
|
||||||
|
#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> DPLL Control
|
||||||
|
// <q> ON Demand
|
||||||
|
// <i> Enable On Demand
|
||||||
|
// <i> If this bit is 0: The DFLL is always on, if enabled.
|
||||||
|
// <i> If this bit is 1: the DFLL will only be running when requested by a peripheral.
|
||||||
|
// <id> fdpll96m_arch_ondemand
|
||||||
|
#ifndef CONF_DPLL_ONDEMAND
|
||||||
|
#define CONF_DPLL_ONDEMAND 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Run In Standby
|
||||||
|
// <i> Run In standby Mode
|
||||||
|
// <i> If this bit is 0: The DFLL is disabled in standby sleep mode.
|
||||||
|
// <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
|
||||||
|
// <id> fdpll96m_arch_runstdby
|
||||||
|
#ifndef CONF_DPLL_RUNSTDBY
|
||||||
|
#define CONF_DPLL_RUNSTDBY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> DPLL Enable
|
||||||
|
// <i> Indicates whether DPLL is enabled or not
|
||||||
|
// <id> fdpll96m_arch_enable
|
||||||
|
#ifndef CONF_DPLL_ENABLE
|
||||||
|
#define CONF_DPLL_ENABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Lock ByPass
|
||||||
|
// <i> Enabling it makes the CLK_FDPLL96M always running otherwise it will be turned off when lock signal is low
|
||||||
|
// <id> fdpll96m_arch_lbypass
|
||||||
|
#ifndef CONF_DPLL_LBYPASS
|
||||||
|
#define CONF_DPLL_LBYPASS 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o>Clock Divider <0-2047>
|
||||||
|
// <i> Clock Division Factor (Applicable if reference clock is XOSC)
|
||||||
|
// <id> fdpll96m_clock_div
|
||||||
|
#ifndef CONF_DPLL_DIV
|
||||||
|
#define CONF_DPLL_DIV 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o>DPLL LDRFRAC<0-15>
|
||||||
|
// <i> Set the fractional part of the frequency multiplier.
|
||||||
|
// <id> fdpll96m_ldrfrac
|
||||||
|
#ifndef CONF_DPLL_LDRFRAC
|
||||||
|
#define CONF_DPLL_LDRFRAC 13
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o>DPLL LDR <0-4095>
|
||||||
|
// <i> Set the integer part of the frequency multiplier.
|
||||||
|
// <id> fdpll96m_ldr
|
||||||
|
#ifndef CONF_DPLL_LDR
|
||||||
|
#define CONF_DPLL_LDR 1463
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
#define CONF_DPLL_LTIME SYSCTRL_DPLLCTRLB_LTIME_NONE_Val
|
||||||
|
#define CONF_DPLL_WUF 0
|
||||||
|
#define CONF_DPLL_LPEN 0
|
||||||
|
#define CONF_DPLL_FILTER SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_SYSCTRL_CONFIG_H
|
||||||
18
Firmware/config/hpl_systick_config.h
Normal file
18
Firmware/config/hpl_systick_config.h
Normal file
@ -0,0 +1,18 @@
|
|||||||
|
/* Auto-generated config file hpl_systick_config.h */
|
||||||
|
#ifndef HPL_SYSTICK_CONFIG_H
|
||||||
|
#define HPL_SYSTICK_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
// <h> Advanced settings
|
||||||
|
// <q> SysTick exception request
|
||||||
|
// <i> Indicates whether the generation of SysTick exception is enabled or not
|
||||||
|
// <id> systick_arch_tickint
|
||||||
|
#ifndef CONF_SYSTICK_TICKINT
|
||||||
|
#define CONF_SYSTICK_TICKINT 0
|
||||||
|
#endif
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_SYSTICK_CONFIG_H
|
||||||
66
Firmware/config/hpl_wdt_config.h
Normal file
66
Firmware/config/hpl_wdt_config.h
Normal file
@ -0,0 +1,66 @@
|
|||||||
|
/* Auto-generated config file hpl_wdt_config.h */
|
||||||
|
#ifndef HPL_WDT_CONFIG_H
|
||||||
|
#define HPL_WDT_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
// <h> Basic settings
|
||||||
|
|
||||||
|
// <o> PER configuration
|
||||||
|
// <0x0=>8 clock cycles
|
||||||
|
// <0x1=>16 clock cycles
|
||||||
|
// <0x2=>32 clock cycles
|
||||||
|
// <0x3=>64 clock cycles
|
||||||
|
// <0x4=>128 clock cycles
|
||||||
|
// <0x5=>256 clock cycles
|
||||||
|
// <0x6=>512 clock cycles
|
||||||
|
// <0x7=>1024 clock cycles
|
||||||
|
// <0x8=>2048 clock cycles
|
||||||
|
// <0x9=>4096 clock cycles
|
||||||
|
// <0xA=>8192 clock cycles
|
||||||
|
// <0xB=>16384 clock cycles
|
||||||
|
// <i> These bits define the watchdog time-out period
|
||||||
|
// <id> wdt_arch_per
|
||||||
|
#ifndef CONF_WDT_PER
|
||||||
|
#define CONF_WDT_PER 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <h> Advanced settings
|
||||||
|
|
||||||
|
// <e> Window mode enable
|
||||||
|
// <i> Watchdog Timer window mode enable
|
||||||
|
// 0: Disabled
|
||||||
|
// 0: Enabled
|
||||||
|
// <id> wdt_arch_window_en
|
||||||
|
#ifndef CONF_WDT_WINDOW_EN
|
||||||
|
#define CONF_WDT_WINDOW_EN 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Window mode timeout period configuration
|
||||||
|
// <0x0=>8 clock cycles
|
||||||
|
// <0x1=>16 clock cycles
|
||||||
|
// <0x2=>32 clock cycles
|
||||||
|
// <0x3=>64 clock cycles
|
||||||
|
// <0x4=>128 clock cycles
|
||||||
|
// <0x5=>256 clock cycles
|
||||||
|
// <0x6=>512 clock cycles
|
||||||
|
// <0x7=>1024 clock cycles
|
||||||
|
// <0x8=>2048 clock cycles
|
||||||
|
// <0x9=>4096 clock cycles
|
||||||
|
// <0xA=>8192 clock cycles
|
||||||
|
// <0xB=>16384 clock cycles
|
||||||
|
// <i> These bits define the watchdog time-out period
|
||||||
|
// <id> wdt_arch_window
|
||||||
|
#ifndef CONF_WDT_WINDOW
|
||||||
|
#define CONF_WDT_WINDOW 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_WDT_CONFIG_H
|
||||||
128
Firmware/config/peripheral_clk_config.h
Normal file
128
Firmware/config/peripheral_clk_config.h
Normal file
@ -0,0 +1,128 @@
|
|||||||
|
/* Auto-generated config file peripheral_clk_config.h */
|
||||||
|
#ifndef PERIPHERAL_CLK_CONFIG_H
|
||||||
|
#define PERIPHERAL_CLK_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
// <y> ADC Clock Source
|
||||||
|
// <id> adc_gclk_selection
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||||
|
|
||||||
|
// <i> Select the clock source for ADC.
|
||||||
|
#ifndef CONF_GCLK_ADC_SRC
|
||||||
|
#define CONF_GCLK_ADC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_GCLK_ADC_FREQUENCY
|
||||||
|
* \brief ADC's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_GCLK_ADC_FREQUENCY
|
||||||
|
#define CONF_GCLK_ADC_FREQUENCY 1000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> EIC Clock Source
|
||||||
|
// <id> eic_gclk_selection
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||||
|
|
||||||
|
// <i> Select the clock source for EIC.
|
||||||
|
#ifndef CONF_GCLK_EIC_SRC
|
||||||
|
#define CONF_GCLK_EIC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_GCLK_EIC_FREQUENCY
|
||||||
|
* \brief EIC's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_GCLK_EIC_FREQUENCY
|
||||||
|
#define CONF_GCLK_EIC_FREQUENCY 1000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_CPU_FREQUENCY
|
||||||
|
* \brief CPU's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_CPU_FREQUENCY
|
||||||
|
#define CONF_CPU_FREQUENCY 1000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> RTC Clock Source
|
||||||
|
// <id> rtc_clk_selection
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||||
|
|
||||||
|
// <i> Select the clock source for RTC.
|
||||||
|
#ifndef CONF_GCLK_RTC_SRC
|
||||||
|
#define CONF_GCLK_RTC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_GCLK_RTC_FREQUENCY
|
||||||
|
* \brief RTC's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_GCLK_RTC_FREQUENCY
|
||||||
|
#define CONF_GCLK_RTC_FREQUENCY 1000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> WDT Clock Source
|
||||||
|
// <id> wdt_gclk_selection
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||||
|
|
||||||
|
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||||
|
|
||||||
|
// <i> Select the clock source for WDT.
|
||||||
|
#ifndef CONF_GCLK_WDT_SRC
|
||||||
|
#define CONF_GCLK_WDT_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* \def CONF_GCLK_WDT_FREQUENCY
|
||||||
|
* \brief WDT's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_GCLK_WDT_FREQUENCY
|
||||||
|
#define CONF_GCLK_WDT_FREQUENCY 1000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // PERIPHERAL_CLK_CONFIG_H
|
||||||
108
Firmware/driver_init.c
Normal file
108
Firmware/driver_init.c
Normal file
@ -0,0 +1,108 @@
|
|||||||
|
/*
|
||||||
|
* Code generated from Atmel Start.
|
||||||
|
*
|
||||||
|
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||||
|
* Please copy examples or other code you want to keep to a separate file
|
||||||
|
* to avoid losing it when reconfiguring.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "driver_init.h"
|
||||||
|
#include <peripheral_clk_config.h>
|
||||||
|
#include <utils.h>
|
||||||
|
#include <hal_init.h>
|
||||||
|
#include <hpl_gclk_base.h>
|
||||||
|
#include <hpl_pm_base.h>
|
||||||
|
|
||||||
|
#include <hpl_adc_base.h>
|
||||||
|
#include <hpl_rtc_base.h>
|
||||||
|
|
||||||
|
struct timer_descriptor TIMER_0;
|
||||||
|
|
||||||
|
struct adc_sync_descriptor ADC_0;
|
||||||
|
|
||||||
|
struct wdt_descriptor WDT_0;
|
||||||
|
|
||||||
|
void ADC_0_PORT_init(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
// Disable digital pin circuitry
|
||||||
|
gpio_set_pin_direction(PIN_ADC, GPIO_DIRECTION_OFF);
|
||||||
|
|
||||||
|
gpio_set_pin_function(PIN_ADC, PINMUX_PA04B_ADC_AIN2);
|
||||||
|
}
|
||||||
|
|
||||||
|
void ADC_0_CLOCK_init(void)
|
||||||
|
{
|
||||||
|
_pm_enable_bus_clock(PM_BUS_APBC, ADC);
|
||||||
|
_gclk_enable_channel(ADC_GCLK_ID, CONF_GCLK_ADC_SRC);
|
||||||
|
}
|
||||||
|
|
||||||
|
void ADC_0_init(void)
|
||||||
|
{
|
||||||
|
ADC_0_CLOCK_init();
|
||||||
|
ADC_0_PORT_init();
|
||||||
|
adc_sync_init(&ADC_0, ADC, (void *)NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
void EXTERNAL_IRQ_0_init(void)
|
||||||
|
{
|
||||||
|
_gclk_enable_channel(EIC_GCLK_ID, CONF_GCLK_EIC_SRC);
|
||||||
|
|
||||||
|
// Set pin direction to input
|
||||||
|
gpio_set_pin_direction(PIN_BUTTON, GPIO_DIRECTION_IN);
|
||||||
|
|
||||||
|
gpio_set_pin_pull_mode(PIN_BUTTON,
|
||||||
|
// <y> Pull configuration
|
||||||
|
// <id> pad_pull_config
|
||||||
|
// <GPIO_PULL_OFF"> Off
|
||||||
|
// <GPIO_PULL_UP"> Pull-up
|
||||||
|
// <GPIO_PULL_DOWN"> Pull-down
|
||||||
|
GPIO_PULL_OFF);
|
||||||
|
|
||||||
|
gpio_set_pin_function(PIN_BUTTON, PINMUX_PA15A_EIC_EXTINT1);
|
||||||
|
|
||||||
|
ext_irq_init();
|
||||||
|
}
|
||||||
|
|
||||||
|
void delay_driver_init(void)
|
||||||
|
{
|
||||||
|
delay_init(SysTick);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief Timer initialization function
|
||||||
|
*
|
||||||
|
* Enables Timer peripheral, clocks and initializes Timer driver
|
||||||
|
*/
|
||||||
|
static void TIMER_0_init(void)
|
||||||
|
{
|
||||||
|
_pm_enable_bus_clock(PM_BUS_APBA, RTC);
|
||||||
|
_gclk_enable_channel(RTC_GCLK_ID, CONF_GCLK_RTC_SRC);
|
||||||
|
timer_init(&TIMER_0, RTC, _rtc_get_timer());
|
||||||
|
}
|
||||||
|
|
||||||
|
void WDT_0_CLOCK_init(void)
|
||||||
|
{
|
||||||
|
_pm_enable_bus_clock(PM_BUS_APBA, WDT);
|
||||||
|
_gclk_enable_channel(WDT_GCLK_ID, CONF_GCLK_WDT_SRC);
|
||||||
|
}
|
||||||
|
|
||||||
|
void WDT_0_init(void)
|
||||||
|
{
|
||||||
|
WDT_0_CLOCK_init();
|
||||||
|
wdt_init(&WDT_0, WDT);
|
||||||
|
}
|
||||||
|
|
||||||
|
void system_init(void)
|
||||||
|
{
|
||||||
|
init_mcu();
|
||||||
|
|
||||||
|
ADC_0_init();
|
||||||
|
EXTERNAL_IRQ_0_init();
|
||||||
|
|
||||||
|
delay_driver_init();
|
||||||
|
|
||||||
|
TIMER_0_init();
|
||||||
|
|
||||||
|
WDT_0_init();
|
||||||
|
}
|
||||||
56
Firmware/driver_init.h
Normal file
56
Firmware/driver_init.h
Normal file
@ -0,0 +1,56 @@
|
|||||||
|
/*
|
||||||
|
* Code generated from Atmel Start.
|
||||||
|
*
|
||||||
|
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||||
|
* Please copy examples or other code you want to keep to a separate file
|
||||||
|
* to avoid losing it when reconfiguring.
|
||||||
|
*/
|
||||||
|
#ifndef DRIVER_INIT_INCLUDED
|
||||||
|
#define DRIVER_INIT_INCLUDED
|
||||||
|
|
||||||
|
#include "atmel_start_pins.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <hal_atomic.h>
|
||||||
|
#include <hal_delay.h>
|
||||||
|
#include <hal_gpio.h>
|
||||||
|
#include <hal_init.h>
|
||||||
|
#include <hal_io.h>
|
||||||
|
#include <hal_sleep.h>
|
||||||
|
|
||||||
|
#include <hal_adc_sync.h>
|
||||||
|
#include <hal_ext_irq.h>
|
||||||
|
|
||||||
|
#include <hal_delay.h>
|
||||||
|
#include <hal_timer.h>
|
||||||
|
|
||||||
|
#include <hal_wdt.h>
|
||||||
|
|
||||||
|
extern struct adc_sync_descriptor ADC_0;
|
||||||
|
|
||||||
|
extern struct timer_descriptor TIMER_0;
|
||||||
|
|
||||||
|
extern struct wdt_descriptor WDT_0;
|
||||||
|
|
||||||
|
void ADC_0_PORT_init(void);
|
||||||
|
void ADC_0_CLOCK_init(void);
|
||||||
|
void ADC_0_init(void);
|
||||||
|
|
||||||
|
void delay_driver_init(void);
|
||||||
|
|
||||||
|
void WDT_0_CLOCK_init(void);
|
||||||
|
void WDT_0_init(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief Perform system initialization, initialize pins and clocks for
|
||||||
|
* peripherals
|
||||||
|
*/
|
||||||
|
void system_init(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif // DRIVER_INIT_INCLUDED
|
||||||
83
Firmware/examples/driver_examples.c
Normal file
83
Firmware/examples/driver_examples.c
Normal file
@ -0,0 +1,83 @@
|
|||||||
|
/*
|
||||||
|
* Code generated from Atmel Start.
|
||||||
|
*
|
||||||
|
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||||
|
* Please copy examples or other code you want to keep to a separate file
|
||||||
|
* to avoid losing it when reconfiguring.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "driver_examples.h"
|
||||||
|
#include "driver_init.h"
|
||||||
|
#include "utils.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Example of using ADC_0 to generate waveform.
|
||||||
|
*/
|
||||||
|
void ADC_0_example(void)
|
||||||
|
{
|
||||||
|
uint8_t buffer[2];
|
||||||
|
|
||||||
|
adc_sync_enable_channel(&ADC_0, 0);
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
adc_sync_read_channel(&ADC_0, 0, buffer, 2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void button_on_PA15_pressed(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Example of using EXTERNAL_IRQ_0
|
||||||
|
*/
|
||||||
|
void EXTERNAL_IRQ_0_example(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
ext_irq_register(PIN_PA15, button_on_PA15_pressed);
|
||||||
|
}
|
||||||
|
|
||||||
|
void delay_example(void)
|
||||||
|
{
|
||||||
|
delay_ms(5000);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct timer_task TIMER_0_task1, TIMER_0_task2;
|
||||||
|
/**
|
||||||
|
* Example of using TIMER_0.
|
||||||
|
*/
|
||||||
|
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void TIMER_0_example(void)
|
||||||
|
{
|
||||||
|
TIMER_0_task1.interval = 100;
|
||||||
|
TIMER_0_task1.cb = TIMER_0_task1_cb;
|
||||||
|
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
|
||||||
|
TIMER_0_task2.interval = 200;
|
||||||
|
TIMER_0_task2.cb = TIMER_0_task2_cb;
|
||||||
|
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
|
||||||
|
|
||||||
|
timer_add_task(&TIMER_0, &TIMER_0_task1);
|
||||||
|
timer_add_task(&TIMER_0, &TIMER_0_task2);
|
||||||
|
timer_start(&TIMER_0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Example of using WDT_0.
|
||||||
|
*/
|
||||||
|
void WDT_0_example(void)
|
||||||
|
{
|
||||||
|
uint32_t clk_rate;
|
||||||
|
uint16_t timeout_period;
|
||||||
|
|
||||||
|
clk_rate = 1000;
|
||||||
|
timeout_period = 4096;
|
||||||
|
wdt_set_timeout_period(&WDT_0, clk_rate, timeout_period);
|
||||||
|
wdt_enable(&WDT_0);
|
||||||
|
}
|
||||||
28
Firmware/examples/driver_examples.h
Normal file
28
Firmware/examples/driver_examples.h
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
/*
|
||||||
|
* Code generated from Atmel Start.
|
||||||
|
*
|
||||||
|
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||||
|
* Please copy examples or other code you want to keep to a separate file
|
||||||
|
* to avoid losing it when reconfiguring.
|
||||||
|
*/
|
||||||
|
#ifndef DRIVER_EXAMPLES_H_INCLUDED
|
||||||
|
#define DRIVER_EXAMPLES_H_INCLUDED
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void ADC_0_example(void);
|
||||||
|
|
||||||
|
void EXTERNAL_IRQ_0_example(void);
|
||||||
|
|
||||||
|
void delay_example(void);
|
||||||
|
|
||||||
|
void TIMER_0_example(void);
|
||||||
|
|
||||||
|
void WDT_0_example(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif // DRIVER_EXAMPLES_H_INCLUDED
|
||||||
BIN
Firmware/gcc/AtmelStart.bin
Executable file
BIN
Firmware/gcc/AtmelStart.bin
Executable file
Binary file not shown.
0
Firmware/gcc/AtmelStart.eep
Executable file
0
Firmware/gcc/AtmelStart.eep
Executable file
BIN
Firmware/gcc/AtmelStart.elf
Executable file
BIN
Firmware/gcc/AtmelStart.elf
Executable file
Binary file not shown.
199
Firmware/gcc/AtmelStart.hex
Normal file
199
Firmware/gcc/AtmelStart.hex
Normal file
@ -0,0 +1,199 @@
|
|||||||
|
:10000000600400204909000045090000450900007E
|
||||||
|
:1000100000000000000000000000000000000000E0
|
||||||
|
:100020000000000000000000000000004509000082
|
||||||
|
:100030000000000000000000450900004509000024
|
||||||
|
:10004000450900004509000045090000E9060000D7
|
||||||
|
:1000500049030000450900004509000000000000B8
|
||||||
|
:1000600045090000450900004509000000000000A6
|
||||||
|
:100070000000000045090000450900004509000096
|
||||||
|
:100080000000000000000000450900000448054B86
|
||||||
|
:1000900010B5834203D0044B002B00D0984710BD0D
|
||||||
|
:1000A000580C0000580C00000000000006480749EA
|
||||||
|
:1000B000091A8B10C90FC91810B5491003D0044B89
|
||||||
|
:1000C000002B00D0984710BD580C0000580C0000C1
|
||||||
|
:1000D0000000000010B5074C2378002B09D1FFF772
|
||||||
|
:1000E000D5FF054B002B02D0044800E000BF0123E0
|
||||||
|
:1000F000237010BD0000002000000000580C00001C
|
||||||
|
:10010000054B10B5002B03D00449054800E000BFA3
|
||||||
|
:10011000FFF7CCFF10BDC046000000000400002027
|
||||||
|
:10012000580C00000122014BC25470471B000020F4
|
||||||
|
:10013000F0B5C0238026802580240E4A0E49DB05B9
|
||||||
|
:10014000F6015E600D4891620D49AD0091625D60FF
|
||||||
|
:1001500090620C48640091625C60906220200A4FBB
|
||||||
|
:1001600091625860976291625E615D615C61586105
|
||||||
|
:10017000F0BDC04600440041004002400002024081
|
||||||
|
:10018000000002C00001024020000240F7B5012635
|
||||||
|
:100190001F27310083B2C2B238408140C020802581
|
||||||
|
:1001A0005209D201C0051418ED0588B22843104D3C
|
||||||
|
:1001B000A16052199062080C8446C02065461B0A53
|
||||||
|
:1001C000000605431F409562BE408025C022B7B29D
|
||||||
|
:1001D000ED053D435B09064FDB01D2059A18DB199B
|
||||||
|
:1001E00096609D62350C28439862A1615661F7BD07
|
||||||
|
:1001F0000044004110B50024094B9847094BE35CCB
|
||||||
|
:10020000002B08D0084B6200D15C9B185878074B34
|
||||||
|
:1002100000020843984701340C2CEDD110BDC046B4
|
||||||
|
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|
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|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user