AtmelStart.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .text 00000c58 00000000 00000000 00001000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .relocate 00000000 20000000 20000000 00001c58 2**0 CONTENTS 2 .bss 00000060 20000000 20000000 00002000 2**2 ALLOC 3 .stack 00000400 20000060 20000060 00002000 2**0 ALLOC 4 .ARM.attributes 00000028 00000000 00000000 00001c58 2**0 CONTENTS, READONLY 5 .comment 00000046 00000000 00000000 00001c80 2**0 CONTENTS, READONLY 6 .debug_info 00015d63 00000000 00000000 00001cc6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 7 .debug_abbrev 00003441 00000000 00000000 00017a29 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 8 .debug_loclists 00003c84 00000000 00000000 0001ae6a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 9 .debug_aranges 000007b0 00000000 00000000 0001eaf0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_rnglists 00000c12 00000000 00000000 0001f2a0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_macro 00010b7c 00000000 00000000 0001feb2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_line 0000c9e8 00000000 00000000 00030a2e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_str 00056810 00000000 00000000 0003d416 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_frame 000010c0 00000000 00000000 00093c28 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_line_str 000000c6 00000000 00000000 00094ce8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 00000000 : void leds_turn_off(uint8_t pos) { leds_state[pos-1] = 0; } void leds_toggle(uint8_t pos) { leds_state[pos-1] = !leds_state[pos-1]; 0: 60 04 00 20 49 09 00 00 45 09 00 00 45 09 00 00 `.. I...E...E... ... if (hri_wdt_get_CTRL_ALWAYSON_bit(dev->hw) || hri_wdt_get_CTRL_ENABLE_bit(dev->hw)) { return ERR_DENIED; } else { /* calc the period cycles corresponding to timeout period */ tmp = (uint64_t)timeout_period * clk_rate; 2c: 45 09 00 00 00 00 00 00 00 00 00 00 45 09 00 00 E...........E... return ERR_INVALID_ARG; } period_cycles = (uint32_t)tmp; /* calc the register value corresponding to period cysles */ switch (period_cycles) { 3c: 45 09 00 00 45 09 00 00 45 09 00 00 45 09 00 00 E...E...E...E... 4c: e9 06 00 00 49 03 00 00 45 09 00 00 45 09 00 00 ....I...E...E... 5c: 00 00 00 00 45 09 00 00 45 09 00 00 45 09 00 00 ....E...E...E... ... break; case WDT_CLK_128CYCLE *WDT_PERIOD_RATE: timeout_period_reg = WDT_PERIOD_128CYCLE; break; case WDT_CLK_256CYCLE *WDT_PERIOD_RATE: timeout_period_reg = WDT_PERIOD_256CYCLE; 74: 45 09 00 00 45 09 00 00 45 09 00 00 00 00 00 00 E...E...E....... switch (period_cycles) { 84: 00 00 00 00 45 09 00 00 ....E... 0000008c : 8c: 4804 ldr r0, [pc, #16] @ (a0 ) break; case WDT_CLK_1024CYCLE *WDT_PERIOD_RATE: timeout_period_reg = WDT_PERIOD_1024CYCLE; break; case WDT_CLK_2048CYCLE *WDT_PERIOD_RATE: timeout_period_reg = WDT_PERIOD_2048CYCLE; 8e: 4b05 ldr r3, [pc, #20] @ (a4 ) switch (period_cycles) { 90: b510 push {r4, lr} 92: 4283 cmp r3, r0 94: d003 beq.n 9e 96: 4b04 ldr r3, [pc, #16] @ (a8 ) 98: 2b00 cmp r3, #0 9a: d000 beq.n 9e 9c: 4798 blx r3 break; case WDT_CLK_8192CYCLE *WDT_PERIOD_RATE: timeout_period_reg = WDT_PERIOD_8192CYCLE; break; case WDT_CLK_16384CYCLE *WDT_PERIOD_RATE: timeout_period_reg = WDT_PERIOD_16384CYCLE; 9e: bd10 pop {r4, pc} switch (period_cycles) { a0: 00000c58 .word 0x00000c58 a4: 00000c58 .word 0x00000c58 } } hri_wdt_write_CONFIG_PER_bf(dev->hw, (uint8_t)timeout_period_reg); return ERR_NONE; a8: 00000000 .word 0x00000000 000000ac : static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) { uint8_t tmp; WDT_CRITICAL_SECTION_ENTER(); tmp = ((Wdt *)hw)->CONFIG.reg; tmp &= ~WDT_CONFIG_PER_Msk; ac: 4806 ldr r0, [pc, #24] @ (c8 ) tmp |= WDT_CONFIG_PER(data); ae: 4907 ldr r1, [pc, #28] @ (cc ) ((Wdt *)hw)->CONFIG.reg = tmp; b0: 1a09 subs r1, r1, r0 } b2: 108b asrs r3, r1, #2 timeout_period_reg = WDT_PERIOD_512CYCLE; b4: 0fc9 lsrs r1, r1, #31 b6: 18c9 adds r1, r1, r3 timeout_period_reg = WDT_PERIOD_64CYCLE; b8: b510 push {r4, lr} ba: 1049 asrs r1, r1, #1 switch (period_cycles) { bc: d003 beq.n c6 be: 4b04 ldr r3, [pc, #16] @ (d0 ) timeout_period_reg = WDT_PERIOD_32CYCLE; c0: 2b00 cmp r3, #0 c2: d000 beq.n c6 timeout_period_reg = WDT_PERIOD_128CYCLE; c4: 4798 blx r3 c6: bd10 pop {r4, pc} timeout_period_reg = WDT_PERIOD_4096CYCLE; c8: 00000c58 .word 0x00000c58 timeout_period_reg = WDT_PERIOD_1024CYCLE; cc: 00000c58 .word 0x00000c58 timeout_period_reg = WDT_PERIOD_8192CYCLE; d0: 00000000 .word 0x00000000 000000d4 <__do_global_dtors_aux>: return ERR_DENIED; d4: b510 push {r4, lr} switch (period_cycles) { d6: 4c07 ldr r4, [pc, #28] @ (f4 <__do_global_dtors_aux+0x20>) d8: 7823 ldrb r3, [r4, #0] da: 2b00 cmp r3, #0 dc: d109 bne.n f2 <__do_global_dtors_aux+0x1e> de: f7ff ffd5 bl 8c e2: 4b05 ldr r3, [pc, #20] @ (f8 <__do_global_dtors_aux+0x24>) e4: 2b00 cmp r3, #0 e6: d002 beq.n ee <__do_global_dtors_aux+0x1a> e8: 4804 ldr r0, [pc, #16] @ (fc <__do_global_dtors_aux+0x28>) ea: e000 b.n ee <__do_global_dtors_aux+0x1a> ec: bf00 nop ee: 2301 movs r3, #1 f0: 7023 strb r3, [r4, #0] f2: bd10 pop {r4, pc} f4: 20000000 .word 0x20000000 f8: 00000000 .word 0x00000000 fc: 00000c58 .word 0x00000c58 00000100 : 100: 4b05 ldr r3, [pc, #20] @ (118 ) 102: b510 push {r4, lr} 104: 2b00 cmp r3, #0 106: d003 beq.n 110 108: 4904 ldr r1, [pc, #16] @ (11c ) 10a: 4805 ldr r0, [pc, #20] @ (120 ) 10c: e000 b.n 110 10e: bf00 nop 110: f7ff ffcc bl ac 114: bd10 pop {r4, pc} 116: 46c0 nop @ (mov r8, r8) 118: 00000000 .word 0x00000000 11c: 20000004 .word 0x20000004 120: 00000c58 .word 0x00000c58 00000124 : leds_state[pos-1] = 1; 124: 2201 movs r2, #1 126: 4b01 ldr r3, [pc, #4] @ (12c ) 128: 54c2 strb r2, [r0, r3] } 12a: 4770 bx lr 12c: 2000001b .word 0x2000001b 00000130 : } void leds_reset() { 130: b5f0 push {r4, r5, r6, r7, lr} ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; } static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) { ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 132: 23c0 movs r3, #192 @ 0xc0 134: 2680 movs r6, #128 @ 0x80 136: 2580 movs r5, #128 @ 0x80 138: 2480 movs r4, #128 @ 0x80 static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, hri_port_wrconfig_reg_t data) { PORT_CRITICAL_SECTION_ENTER(); ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 13a: 4a0e ldr r2, [pc, #56] @ (174 ) 13c: 490e ldr r1, [pc, #56] @ (178 ) ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 13e: 05db lsls r3, r3, #23 140: 01f6 lsls r6, r6, #7 142: 605e str r6, [r3, #4] ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 144: 480d ldr r0, [pc, #52] @ (17c ) 146: 6291 str r1, [r2, #40] @ 0x28 148: 490d ldr r1, [pc, #52] @ (180 ) ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 14a: 00ad lsls r5, r5, #2 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 14c: 6291 str r1, [r2, #40] @ 0x28 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 14e: 605d str r5, [r3, #4] ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 150: 6290 str r0, [r2, #40] @ 0x28 152: 480c ldr r0, [pc, #48] @ (184 ) ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 154: 0064 lsls r4, r4, #1 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 156: 6291 str r1, [r2, #40] @ 0x28 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 158: 605c str r4, [r3, #4] ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 15a: 6290 str r0, [r2, #40] @ 0x28 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 15c: 2020 movs r0, #32 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 15e: 4f0a ldr r7, [pc, #40] @ (188 ) 160: 6291 str r1, [r2, #40] @ 0x28 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 162: 6058 str r0, [r3, #4] ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 164: 6297 str r7, [r2, #40] @ 0x28 166: 6291 str r1, [r2, #40] @ 0x28 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; 168: 615e str r6, [r3, #20] 16a: 615d str r5, [r3, #20] 16c: 615c str r4, [r3, #20] 16e: 6158 str r0, [r3, #20] // all pins on one level gpio_set_pin_level(PIN_LEDS1, 0); gpio_set_pin_level(PIN_LEDS2, 0); gpio_set_pin_level(PIN_LEDS3, 0); gpio_set_pin_level(PIN_LEDS4, 0); } 170: bdf0 pop {r4, r5, r6, r7, pc} 172: 46c0 nop @ (mov r8, r8) 174: 41004400 .word 0x41004400 178: 40024000 .word 0x40024000 17c: 40020200 .word 0x40020200 180: c0020000 .word 0xc0020000 184: 40020100 .word 0x40020100 188: 40020020 .word 0x40020020 0000018c : void leds_set_pins(led_t l) { 18c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} * GPIO_DIRECTION_OFF = Disables the pin * (low power state) */ static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) { _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); 18e: 2601 movs r6, #1 190: 271f movs r7, #31 192: 0031 movs r1, r6 194: b283 uxth r3, r0 196: b2c2 uxtb r2, r0 198: 4038 ands r0, r7 19a: 4081 lsls r1, r0 ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; 19c: 20c0 movs r0, #192 @ 0xc0 | ((mask & 0xffff0000) >> 16)); break; case GPIO_DIRECTION_OUT: hri_port_set_DIR_reg(PORT_IOBUS, port, mask); hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); 19e: 2580 movs r5, #128 @ 0x80 1a0: 0952 lsrs r2, r2, #5 1a2: 01d2 lsls r2, r2, #7 1a4: 05c0 lsls r0, r0, #23 1a6: 1814 adds r4, r2, r0 1a8: 05ed lsls r5, r5, #23 1aa: b288 uxth r0, r1 1ac: 4328 orrs r0, r5 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 1ae: 4d10 ldr r5, [pc, #64] @ (1f0 ) ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; 1b0: 60a1 str r1, [r4, #8] ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 1b2: 1952 adds r2, r2, r5 1b4: 6290 str r0, [r2, #40] @ 0x28 hri_port_write_WRCONFIG_reg( PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); 1b6: 0c08 lsrs r0, r1, #16 1b8: 4684 mov ip, r0 hri_port_write_WRCONFIG_reg( 1ba: 20c0 movs r0, #192 @ 0xc0 1bc: 4665 mov r5, ip 1be: 0a1b lsrs r3, r3, #8 1c0: 0600 lsls r0, r0, #24 1c2: 4305 orrs r5, r0 1c4: 401f ands r7, r3 1c6: 6295 str r5, [r2, #40] @ 0x28 1c8: 40be lsls r6, r7 hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); 1ca: 2580 movs r5, #128 @ 0x80 ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; 1cc: 22c0 movs r2, #192 @ 0xc0 1ce: b2b7 uxth r7, r6 1d0: 05ed lsls r5, r5, #23 1d2: 433d orrs r5, r7 1d4: 095b lsrs r3, r3, #5 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 1d6: 4f06 ldr r7, [pc, #24] @ (1f0 ) ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; 1d8: 01db lsls r3, r3, #7 1da: 05d2 lsls r2, r2, #23 1dc: 189a adds r2, r3, r2 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 1de: 19db adds r3, r3, r7 ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; 1e0: 6096 str r6, [r2, #8] ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 1e2: 629d str r5, [r3, #40] @ 0x28 PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); 1e4: 0c35 lsrs r5, r6, #16 hri_port_write_WRCONFIG_reg( 1e6: 4328 orrs r0, r5 1e8: 6298 str r0, [r3, #40] @ 0x28 ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; 1ea: 61a1 str r1, [r4, #24] ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; 1ec: 6156 str r6, [r2, #20] gpio_set_pin_direction(l.pin_high, GPIO_DIRECTION_OUT); gpio_set_pin_direction(l.pin_low, GPIO_DIRECTION_OUT); gpio_set_pin_level(l.pin_high, 1); gpio_set_pin_level(l.pin_low, 0); } 1ee: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc} 1f0: 41004400 .word 0x41004400 000001f4 : void leds_draw() { 1f4: b510 push {r4, lr} int i; for (i = 0; i < ARRAY_SIZE(leds_data); i++) { 1f6: 2400 movs r4, #0 leds_reset(); 1f8: 4b09 ldr r3, [pc, #36] @ (220 ) 1fa: 4798 blx r3 // check if led needs to be lit if (leds_state[i]) { 1fc: 4b09 ldr r3, [pc, #36] @ (224 ) 1fe: 5ce3 ldrb r3, [r4, r3] 200: 2b00 cmp r3, #0 202: d008 beq.n 216 leds_set_pins(leds_data[i]); 204: 4b08 ldr r3, [pc, #32] @ (228 ) 206: 0062 lsls r2, r4, #1 208: 5cd1 ldrb r1, [r2, r3] 20a: 189b adds r3, r3, r2 20c: 7858 ldrb r0, [r3, #1] 20e: 4b07 ldr r3, [pc, #28] @ (22c ) 210: 0200 lsls r0, r0, #8 212: 4308 orrs r0, r1 214: 4798 blx r3 for (i = 0; i < ARRAY_SIZE(leds_data); i++) { 216: 3401 adds r4, #1 218: 2c0c cmp r4, #12 21a: d1ed bne.n 1f8 } } } 21c: bd10 pop {r4, pc} 21e: 46c0 nop @ (mov r8, r8) 220: 00000131 .word 0x00000131 224: 2000001c .word 0x2000001c 228: 00000b5c .word 0x00000b5c 22c: 0000018d .word 0x0000018d 00000230 <_delay_init>: | (1 << SysTick_CTRL_CLKSOURCE_Pos); } /** * \brief Initialize delay functionality */ void _delay_init(void *const hw) 230: 4b02 ldr r3, [pc, #8] @ (23c <_delay_init+0xc>) 232: 4a03 ldr r2, [pc, #12] @ (240 <_delay_init+0x10>) 234: 605a str r2, [r3, #4] 236: 2205 movs r2, #5 238: 601a str r2, [r3, #0] 23a: 4770 bx lr 23c: e000e010 .word 0xe000e010 240: 00ffffff .word 0x00ffffff 00000244 <_delay_cycles>: } /** * \brief Delay loop to delay n number of cycles */ void _delay_cycles(void *const hw, uint32_t cycles) { 244: b570 push {r4, r5, r6, lr} uint32_t buf = cycles; while (n--) { SysTick->LOAD = 0xFFFFFF; SysTick->VAL = 0xFFFFFF; while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) 246: 2580 movs r5, #128 @ 0x80 uint8_t n = cycles >> 24; 248: 0e0b lsrs r3, r1, #24 24a: 4a0c ldr r2, [pc, #48] @ (27c <_delay_cycles+0x38>) SysTick->LOAD = 0xFFFFFF; 24c: 4c0c ldr r4, [pc, #48] @ (280 <_delay_cycles+0x3c>) uint8_t n = cycles >> 24; 24e: b2d8 uxtb r0, r3 while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) 250: 026d lsls r5, r5, #9 while (n--) { 252: 3801 subs r0, #1 254: b2c0 uxtb r0, r0 256: 28ff cmp r0, #255 @ 0xff 258: d10a bne.n 270 <_delay_cycles+0x2c> 25a: 0618 lsls r0, r3, #24 25c: 1a1b subs r3, r3, r0 25e: 1859 adds r1, r3, r1 buf -= 0xFFFFFF; } SysTick->LOAD = buf; SysTick->VAL = buf; while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) 260: 2380 movs r3, #128 @ 0x80 SysTick->LOAD = buf; 262: 6051 str r1, [r2, #4] while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) 264: 025b lsls r3, r3, #9 SysTick->VAL = buf; 266: 6091 str r1, [r2, #8] while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) 268: 6811 ldr r1, [r2, #0] 26a: 4219 tst r1, r3 26c: d0fc beq.n 268 <_delay_cycles+0x24> ; } 26e: bd70 pop {r4, r5, r6, pc} SysTick->LOAD = 0xFFFFFF; 270: 6054 str r4, [r2, #4] SysTick->VAL = 0xFFFFFF; 272: 6094 str r4, [r2, #8] while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) 274: 6816 ldr r6, [r2, #0] 276: 422e tst r6, r5 278: d0fc beq.n 274 <_delay_cycles+0x30> 27a: e7ea b.n 252 <_delay_cycles+0xe> 27c: e000e010 .word 0xe000e010 280: 00ffffff .word 0x00ffffff 00000284 <_wdt_init>: { 284: b510 push {r4, lr} 286: 1e04 subs r4, r0, #0 ASSERT(dev && dev->hw); 288: d003 beq.n 292 <_wdt_init+0xe> 28a: 6800 ldr r0, [r0, #0] 28c: 1e43 subs r3, r0, #1 28e: 4198 sbcs r0, r3 290: b2c0 uxtb r0, r0 292: 224f movs r2, #79 @ 0x4f 294: 4b0b ldr r3, [pc, #44] @ (2c4 <_wdt_init+0x40>) 296: 490c ldr r1, [pc, #48] @ (2c8 <_wdt_init+0x44>) 298: 4798 blx r3 if (hri_wdt_get_CTRL_ALWAYSON_bit(dev->hw) || hri_wdt_get_CTRL_ENABLE_bit(dev->hw)) { 29a: 6823 ldr r3, [r4, #0] tmp = ((Wdt *)hw)->CTRL.reg; 29c: 781a ldrb r2, [r3, #0] 29e: 09d2 lsrs r2, r2, #7 2a0: d10d bne.n 2be <_wdt_init+0x3a> tmp = ((Wdt *)hw)->CTRL.reg; 2a2: 781a ldrb r2, [r3, #0] return (bool)tmp; 2a4: 0792 lsls r2, r2, #30 2a6: 0fd0 lsrs r0, r2, #31 2a8: 2a00 cmp r2, #0 2aa: db08 blt.n 2be <_wdt_init+0x3a> ((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_WEN; 2ac: 2104 movs r1, #4 2ae: 781a ldrb r2, [r3, #0] 2b0: 438a bics r2, r1 2b2: 701a strb r2, [r3, #0] tmp = ((Wdt *)hw)->CONFIG.reg; 2b4: 785a ldrb r2, [r3, #1] tmp &= ~WDT_CONFIG_PER_Msk; 2b6: 310b adds r1, #11 2b8: 438a bics r2, r1 ((Wdt *)hw)->CONFIG.reg = tmp; 2ba: 705a strb r2, [r3, #1] } 2bc: bd10 pop {r4, pc} return ERR_DENIED; 2be: 2011 movs r0, #17 2c0: 4240 negs r0, r0 2c2: e7fb b.n 2bc <_wdt_init+0x38> 2c4: 000005b5 .word 0x000005b5 2c8: 00000b74 .word 0x00000b74 000002cc : typedef uint8_t hri_eic_nmiflag_reg_t; typedef uint8_t hri_eic_status_reg_t; static inline void hri_eic_wait_for_sync(const void *const hw) { while (((const Eic *)hw)->STATUS.bit.SYNCBUSY) 2cc: 4a02 ldr r2, [pc, #8] @ (2d8 ) 2ce: 7853 ldrb r3, [r2, #1] 2d0: 09db lsrs r3, r3, #7 2d2: d1fc bne.n 2ce ; } 2d4: 4770 bx lr 2d6: 46c0 nop @ (mov r8, r8) 2d8: 40001800 .word 0x40001800 000002dc <_ext_irq_init>: /** * \brief Initialize external interrupt module */ int32_t _ext_irq_init(void (*cb)(const uint32_t pin)) { 2dc: b5f8 push {r3, r4, r5, r6, r7, lr} static inline hri_eic_ctrl_reg_t hri_eic_get_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) { uint8_t tmp; hri_eic_wait_for_sync(hw); tmp = ((Eic *)hw)->CTRL.reg; 2de: 4c15 ldr r4, [pc, #84] @ (334 <_ext_irq_init+0x58>) hri_eic_wait_for_sync(EIC); 2e0: 4d15 ldr r5, [pc, #84] @ (338 <_ext_irq_init+0x5c>) { 2e2: 0007 movs r7, r0 hri_eic_wait_for_sync(EIC); 2e4: 47a8 blx r5 hri_eic_wait_for_sync(hw); 2e6: 47a8 blx r5 tmp = ((Eic *)hw)->CTRL.reg; 2e8: 7823 ldrb r3, [r4, #0] if (hri_eic_get_CTRL_reg(EIC, EIC_CTRL_ENABLE)) { 2ea: 079b lsls r3, r3, #30 2ec: d503 bpl.n 2f6 <_ext_irq_init+0x1a> } static inline void hri_eic_write_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->CTRL.reg = data; 2ee: 2300 movs r3, #0 2f0: 7023 strb r3, [r4, #0] hri_eic_wait_for_sync(hw); 2f2: 47a8 blx r5 hri_eic_write_CTRL_reg(EIC, 0); hri_eic_wait_for_sync(EIC); 2f4: 47a8 blx r5 ((Eic *)hw)->CTRL.reg = data; 2f6: 2301 movs r3, #1 } static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->NMICTRL.reg = data; 2f8: 2600 movs r6, #0 ((Eic *)hw)->CTRL.reg = data; 2fa: 7023 strb r3, [r4, #0] hri_eic_wait_for_sync(hw); 2fc: 47a8 blx r5 } hri_eic_write_CTRL_reg(EIC, EIC_CTRL_SWRST); hri_eic_wait_for_sync(EIC); 2fe: 47a8 blx r5 ((Eic *)hw)->CTRL.reg |= EIC_CTRL_ENABLE; 300: 2302 movs r3, #2 ((Eic *)hw)->NMICTRL.reg = data; 302: 70a6 strb r6, [r4, #2] } static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->EVCTRL.reg = data; 304: 6066 str r6, [r4, #4] } static inline void hri_eic_write_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->WAKEUP.reg = data; 306: 6166 str r6, [r4, #20] } static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->CONFIG[index].reg = data; 308: 61a6 str r6, [r4, #24] ((Eic *)hw)->CTRL.reg |= EIC_CTRL_ENABLE; 30a: 7822 ldrb r2, [r4, #0] 30c: 4313 orrs r3, r2 30e: 7023 strb r3, [r4, #0] hri_eic_wait_for_sync(hw); 310: 47a8 blx r5 */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 312: 2310 movs r3, #16 314: 4909 ldr r1, [pc, #36] @ (33c <_ext_irq_init+0x60>) 316: 4a0a ldr r2, [pc, #40] @ (340 <_ext_irq_init+0x64>) 318: 67cb str r3, [r1, #124] @ 0x7c \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 31a: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 31e: f3bf 8f6f isb sy */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 322: 21c0 movs r1, #192 @ 0xc0 324: 0049 lsls r1, r1, #1 326: 5053 str r3, [r2, r1] NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 328: 6013 str r3, [r2, #0] NVIC_DisableIRQ(EIC_IRQn); NVIC_ClearPendingIRQ(EIC_IRQn); NVIC_EnableIRQ(EIC_IRQn); callback = cb; 32a: 4b06 ldr r3, [pc, #24] @ (344 <_ext_irq_init+0x68>) return ERR_NONE; } 32c: 0030 movs r0, r6 callback = cb; 32e: 601f str r7, [r3, #0] } 330: bdf8 pop {r3, r4, r5, r6, r7, pc} 332: 46c0 nop @ (mov r8, r8) 334: 40001800 .word 0x40001800 338: 000002cd .word 0x000002cd 33c: e000e104 .word 0xe000e104 340: e000e100 .word 0xe000e100 344: 20000028 .word 0x20000028 00000348 : /** * \brief EIC interrupt handler */ void EIC_Handler(void) { 348: b5f0 push {r4, r5, r6, r7, lr} return ((Eic *)hw)->INTFLAG.reg; 34a: 4d27 ldr r5, [pc, #156] @ (3e8 ) 34c: b085 sub sp, #20 34e: 692b ldr r3, [r5, #16] return ((Eic *)hw)->INTENSET.reg; 350: 68ea ldr r2, [r5, #12] int8_t pos; uint32_t pin = INVALID_PIN_NUMBER; hri_eic_clear_INTFLAG_reg(EIC, flags); ASSERT(callback); 352: 4e26 ldr r6, [pc, #152] @ (3ec ) volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC) & hri_eic_read_INTEN_reg(EIC); 354: 4013 ands r3, r2 356: 9303 str r3, [sp, #12] hri_eic_clear_INTFLAG_reg(EIC, flags); 358: 9b03 ldr r3, [sp, #12] ASSERT(callback); 35a: 6830 ldr r0, [r6, #0] ((Eic *)hw)->INTFLAG.reg = mask; 35c: 612b str r3, [r5, #16] 35e: 1e43 subs r3, r0, #1 360: 4198 sbcs r0, r3 362: 22c1 movs r2, #193 @ 0xc1 364: 4b22 ldr r3, [pc, #136] @ (3f0 ) 366: 4923 ldr r1, [pc, #140] @ (3f4 ) 368: b2c0 uxtb r0, r0 36a: 4798 blx r3 uint32_t pin = INVALID_PIN_NUMBER; 36c: 2301 movs r3, #1 36e: 425b negs r3, r3 370: 9300 str r3, [sp, #0] while (flags) { 372: 9b03 ldr r3, [sp, #12] 374: 2b00 cmp r3, #0 376: d101 bne.n 37c pos = ffs(flags) - 1; } flags = hri_eic_read_INTFLAG_reg(EIC) & hri_eic_read_INTEN_reg(EIC); hri_eic_clear_INTFLAG_reg(EIC, flags); } } 378: b005 add sp, #20 37a: bdf0 pop {r4, r5, r6, r7, pc} pos = ffs(flags) - 1; 37c: 9803 ldr r0, [sp, #12] 37e: 4f1e ldr r7, [pc, #120] @ (3f8 ) pos = ffs(flags) - 1; 380: 47b8 blx r7 382: 3801 subs r0, #1 384: b244 sxtb r4, r0 while (-1 != pos) { 386: 1c63 adds r3, r4, #1 388: d106 bne.n 398 return ((Eic *)hw)->INTFLAG.reg; 38a: 692b ldr r3, [r5, #16] return ((Eic *)hw)->INTENSET.reg; 38c: 68ea ldr r2, [r5, #12] flags = hri_eic_read_INTFLAG_reg(EIC) & hri_eic_read_INTEN_reg(EIC); 38e: 4013 ands r3, r2 390: 9303 str r3, [sp, #12] hri_eic_clear_INTFLAG_reg(EIC, flags); 392: 9b03 ldr r3, [sp, #12] ((Eic *)hw)->INTFLAG.reg = mask; 394: 612b str r3, [r5, #16] } 396: e7ec b.n 372 if (_map[middle].extint == pos) { 398: 4b18 ldr r3, [pc, #96] @ (3fc ) uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; 39a: 2001 movs r0, #1 39c: 2200 movs r2, #0 if (_map[middle].extint == pos) { 39e: 469c mov ip, r3 middle = (upper + lower) >> 1; 3a0: 1883 adds r3, r0, r2 3a2: 105b asrs r3, r3, #1 3a4: b2d9 uxtb r1, r3 3a6: 9101 str r1, [sp, #4] if (_map[middle].extint == pos) { 3a8: 4661 mov r1, ip 3aa: 00db lsls r3, r3, #3 3ac: 5c5b ldrb r3, [r3, r1] 3ae: 42a3 cmp r3, r4 3b0: d10b bne.n 3ca callback(pin); 3b2: 6833 ldr r3, [r6, #0] 3b4: 200f movs r0, #15 3b6: 4798 blx r3 3b8: 230f movs r3, #15 3ba: 9300 str r3, [sp, #0] flags &= ~(1ul << pos); 3bc: 2201 movs r2, #1 3be: 40a2 lsls r2, r4 3c0: 9b03 ldr r3, [sp, #12] 3c2: 4393 bics r3, r2 3c4: 9303 str r3, [sp, #12] pos = ffs(flags) - 1; 3c6: 9803 ldr r0, [sp, #12] 3c8: e7da b.n 380 lower = middle + 1; 3ca: 9901 ldr r1, [sp, #4] if (_map[middle].extint < pos) { 3cc: 42a3 cmp r3, r4 3ce: da07 bge.n 3e0 lower = middle + 1; 3d0: 3101 adds r1, #1 3d2: b2ca uxtb r2, r1 while (upper >= lower) { 3d4: 4282 cmp r2, r0 3d6: d9e3 bls.n 3a0 if (INVALID_PIN_NUMBER != pin) { 3d8: 9b00 ldr r3, [sp, #0] 3da: 3301 adds r3, #1 3dc: d1e9 bne.n 3b2 3de: e7ed b.n 3bc upper = middle - 1; 3e0: 3901 subs r1, #1 3e2: b2c8 uxtb r0, r1 3e4: e7f6 b.n 3d4 3e6: 46c0 nop @ (mov r8, r8) 3e8: 40001800 .word 0x40001800 3ec: 20000028 .word 0x20000028 3f0: 000005b5 .word 0x000005b5 3f4: 00000b89 .word 0x00000b89 3f8: 00000ac5 .word 0x00000ac5 3fc: 00000c30 .word 0x00000c30 00000400 : * \param[in] head The pointer to the head of timer task list * \param[in] task The pointer to task to add * \param[in] time Current timer time */ static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) { 400: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} * \return A pointer to the head of the given list or NULL if the list is * empty */ static inline void *list_get_head(const struct list_descriptor *const list) { return (void *)list->head; 402: 6805 ldr r5, [r0, #0] struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); if (!head) { 404: 2d00 cmp r5, #0 406: d102 bne.n 40e list_insert_as_head(list, new_task); 408: 4b11 ldr r3, [pc, #68] @ (450 ) } if (it == head) { list_insert_as_head(list, new_task); } else { list_insert_after(prev, new_task); 40a: 4798 blx r3 } } 40c: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc} time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 40e: 2601 movs r6, #1 for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { 410: 002c movs r4, r5 struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); 412: 2700 movs r7, #0 if (time_left >= new_task->interval) 414: 688b ldr r3, [r1, #8] 416: 9300 str r3, [sp, #0] time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 418: 1ab3 subs r3, r6, r2 41a: 9301 str r3, [sp, #4] time_left = it->interval - (time - it->time_label); 41c: 68a6 ldr r6, [r4, #8] if (it->time_label <= time) { 41e: 6863 ldr r3, [r4, #4] time_left = it->interval - (time - it->time_label); 420: 46b4 mov ip, r6 if (it->time_label <= time) { 422: 4293 cmp r3, r2 424: d80d bhi.n 442 time_left = it->interval - (time - it->time_label); 426: 4463 add r3, ip 428: 1a9b subs r3, r3, r2 if (time_left >= new_task->interval) 42a: 9e00 ldr r6, [sp, #0] 42c: 429e cmp r6, r3 42e: d90c bls.n 44a * \return A pointer to the next list element or NULL if there is not next * element */ static inline void *list_get_next_element(const void *const element) { return element ? ((struct list_element *)element)->next : NULL; 430: 6823 ldr r3, [r4, #0] for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { 432: 0027 movs r7, r4 434: 2b00 cmp r3, #0 436: d102 bne.n 43e list_insert_after(prev, new_task); 438: 0038 movs r0, r7 43a: 4b06 ldr r3, [pc, #24] @ (454 ) 43c: e7e5 b.n 40a 43e: 001c movs r4, r3 440: e7ec b.n 41c time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 442: 9e01 ldr r6, [sp, #4] 444: 18f3 adds r3, r6, r3 446: 4463 add r3, ip 448: e7ef b.n 42a if (it == head) { 44a: 42a5 cmp r5, r4 44c: d0dc beq.n 408 44e: e7f3 b.n 438 450: 00000645 .word 0x00000645 454: 00000671 .word 0x00000671 00000458 : /** * \internal Process interrupts */ static void timer_process_counted(struct _timer_device *device) { 458: b5f8 push {r3, r4, r5, r6, r7, lr} struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); uint32_t time = ++timer->time; 45a: 6906 ldr r6, [r0, #16] if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { 45c: 7e03 ldrb r3, [r0, #24] uint32_t time = ++timer->time; 45e: 3601 adds r6, #1 { 460: 0004 movs r4, r0 return (void *)list->head; 462: 6945 ldr r5, [r0, #20] uint32_t time = ++timer->time; 464: 6106 str r6, [r0, #16] if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { 466: 07db lsls r3, r3, #31 468: d402 bmi.n 470 46a: 7e03 ldrb r3, [r0, #24] 46c: 079b lsls r3, r3, #30 46e: d517 bpl.n 4a0 timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; 470: 2302 movs r3, #2 472: 7e22 ldrb r2, [r4, #24] 474: 4313 orrs r3, r2 476: 7623 strb r3, [r4, #24] } it = (struct timer_task *)list_get_head(&timer->tasks); tmp->cb(tmp); } } 478: bdf8 pop {r3, r4, r5, r6, r7, pc} list_remove_head(&timer->tasks); 47a: 0027 movs r7, r4 47c: 3714 adds r7, #20 47e: 4b0c ldr r3, [pc, #48] @ (4b0 ) 480: 0038 movs r0, r7 482: 4798 blx r3 if (TIMER_TASK_REPEAT == tmp->mode) { 484: 7c2b ldrb r3, [r5, #16] 486: 2b01 cmp r3, #1 488: d105 bne.n 496 timer_add_timer_task(&timer->tasks, tmp, time); 48a: 0032 movs r2, r6 48c: 0029 movs r1, r5 48e: 0038 movs r0, r7 490: 4b08 ldr r3, [pc, #32] @ (4b4 ) tmp->time_label = time; 492: 606e str r6, [r5, #4] timer_add_timer_task(&timer->tasks, tmp, time); 494: 4798 blx r3 496: 6967 ldr r7, [r4, #20] tmp->cb(tmp); 498: 0028 movs r0, r5 49a: 68eb ldr r3, [r5, #12] 49c: 4798 blx r3 it = (struct timer_task *)list_get_head(&timer->tasks); 49e: 003d movs r5, r7 while (it && ((time - it->time_label) >= it->interval)) { 4a0: 2d00 cmp r5, #0 4a2: d0e9 beq.n 478 4a4: 686b ldr r3, [r5, #4] 4a6: 68aa ldr r2, [r5, #8] 4a8: 1af3 subs r3, r6, r3 4aa: 4293 cmp r3, r2 4ac: d2e5 bcs.n 47a 4ae: e7e3 b.n 478 4b0: 00000679 .word 0x00000679 4b4: 00000401 .word 0x00000401 000004b8 : { 4b8: b570 push {r4, r5, r6, lr} 4ba: 000d movs r5, r1 ASSERT(descr && hw); 4bc: 002b movs r3, r5 { 4be: 0004 movs r4, r0 ASSERT(descr && hw); 4c0: 1e5a subs r2, r3, #1 4c2: 4193 sbcs r3, r2 4c4: 1e42 subs r2, r0, #1 4c6: 4190 sbcs r0, r2 4c8: 4906 ldr r1, [pc, #24] @ (4e4 ) 4ca: 223b movs r2, #59 @ 0x3b 4cc: 4018 ands r0, r3 4ce: 4b06 ldr r3, [pc, #24] @ (4e8 ) 4d0: 4798 blx r3 _timer_init(&descr->device, hw); 4d2: 0029 movs r1, r5 4d4: 0020 movs r0, r4 4d6: 4b05 ldr r3, [pc, #20] @ (4ec ) 4d8: 4798 blx r3 descr->time = 0; 4da: 2000 movs r0, #0 descr->device.timer_cb.period_expired = timer_process_counted; 4dc: 4b04 ldr r3, [pc, #16] @ (4f0 ) descr->time = 0; 4de: 6120 str r0, [r4, #16] descr->device.timer_cb.period_expired = timer_process_counted; 4e0: 6023 str r3, [r4, #0] } 4e2: bd70 pop {r4, r5, r6, pc} 4e4: 00000b9e .word 0x00000b9e 4e8: 000005b5 .word 0x000005b5 4ec: 00000691 .word 0x00000691 4f0: 00000459 .word 0x00000459 000004f4 : /** * \brief Initialize Delay driver */ void delay_init(void *const hw) { 4f4: b510 push {r4, lr} _delay_init(hardware = hw); 4f6: 4b02 ldr r3, [pc, #8] @ (500 ) 4f8: 6018 str r0, [r3, #0] 4fa: 4b02 ldr r3, [pc, #8] @ (504 ) 4fc: 4798 blx r3 } 4fe: bd10 pop {r4, pc} 500: 2000002c .word 0x2000002c 504: 00000231 .word 0x00000231 00000508 : /** * \brief Perform delay in ms */ void delay_ms(const uint16_t ms) { _delay_cycles(hardware, _get_cycles_for_ms(ms)); 508: 4b04 ldr r3, [pc, #16] @ (51c ) { 50a: b510 push {r4, lr} _delay_cycles(hardware, _get_cycles_for_ms(ms)); 50c: 681c ldr r4, [r3, #0] 50e: 4b04 ldr r3, [pc, #16] @ (520 ) 510: 4798 blx r3 512: 0001 movs r1, r0 514: 4b03 ldr r3, [pc, #12] @ (524 ) 516: 0020 movs r0, r4 518: 4798 blx r3 } 51a: bd10 pop {r4, pc} 51c: 2000002c .word 0x2000002c 520: 000005ad .word 0x000005ad 524: 00000245 .word 0x00000245 00000528 <_sysctrl_init_sources>: } static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_CALIB_bf(const void *const hw) { uint32_t tmp; tmp = ((Sysctrl *)hw)->OSC8M.reg; 528: 4b0d ldr r3, [pc, #52] @ (560 <_sysctrl_init_sources+0x38>) hri_sysctrl_write_OSC8M_reg(hw, SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) | #if CONF_OSC8M_OVERWRITE_CALIBRATION == 1 SYSCTRL_OSC8M_CALIB(CONF_OSC8M_CALIB) | #else SYSCTRL_OSC8M_CALIB(calib) | 52a: 480e ldr r0, [pc, #56] @ (564 <_sysctrl_init_sources+0x3c>) 52c: 6a19 ldr r1, [r3, #32] } static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_FRANGE_bf(const void *const hw) { uint32_t tmp; tmp = ((Sysctrl *)hw)->OSC8M.reg; 52e: 6a1a ldr r2, [r3, #32] 530: 4001 ands r1, r0 SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) | 532: 0f92 lsrs r2, r2, #30 534: 0792 lsls r2, r2, #30 536: 430a orrs r2, r1 hri_sysctrl_write_OSC8M_reg(hw, 538: 490b ldr r1, [pc, #44] @ (568 <_sysctrl_init_sources+0x40>) 53a: 430a orrs r2, r1 } static inline void hri_sysctrl_write_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t data) { SYSCTRL_CRITICAL_SECTION_ENTER(); ((Sysctrl *)hw)->OSC8M.reg = data; 53c: 621a str r2, [r3, #32] ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; 53e: 2202 movs r2, #2 540: 6999 ldr r1, [r3, #24] 542: 430a orrs r2, r1 tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos; 544: 211f movs r1, #31 ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; 546: 619a str r2, [r3, #24] tmp = ((Sysctrl *)hw)->OSCULP32K.reg; 548: 7f1a ldrb r2, [r3, #28] tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos; 54a: 400a ands r2, r1 ((Sysctrl *)hw)->OSCULP32K.reg = data; 54c: 771a strb r2, [r3, #28] #endif #endif #if CONF_OSC8M_CONFIG == 1 #if CONF_OSC8M_ENABLE == 1 while (!hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(hw)) 54e: 2208 movs r2, #8 return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY) >> SYSCTRL_PCLKSR_OSC8MRDY_Pos; 550: 68d9 ldr r1, [r3, #12] 552: 4211 tst r1, r2 554: d0fc beq.n 550 <_sysctrl_init_sources+0x28> ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ONDEMAND; 556: 2280 movs r2, #128 @ 0x80 558: 6a19 ldr r1, [r3, #32] 55a: 430a orrs r2, r1 55c: 621a str r2, [r3, #32] hri_sysctrl_set_OSC8M_ONDEMAND_bit(hw); #endif #endif (void)calib, (void)hw; } 55e: 4770 bx lr 560: 40000800 .word 0x40000800 564: 0fff0000 .word 0x0fff0000 568: 00000302 .word 0x00000302 0000056c <_sysctrl_init_referenced_generators>: ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; 56c: 2102 movs r1, #2 56e: 4a02 ldr r2, [pc, #8] @ (578 <_sysctrl_init_referenced_generators+0xc>) 570: 6993 ldr r3, [r2, #24] 572: 438b bics r3, r1 574: 6193 str r3, [r2, #24] /* Disable after all possible configurations needs sync written. */ hri_sysctrl_clear_OSC32K_ENABLE_bit(hw); #endif (void)hw; } 576: 4770 bx lr 578: 40000800 .word 0x40000800 0000057c <_init_chip>: } static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) { NVMCTRL_CRITICAL_SECTION_ENTER(); ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); 57c: 4b06 ldr r3, [pc, #24] @ (598 <_init_chip+0x1c>) /** * \brief Initialize the hardware abstraction layer */ void _init_chip(void) { 57e: b510 push {r4, lr} 580: 685a ldr r2, [r3, #4] 582: 605a str r2, [r3, #4] hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); _pm_init(); 584: 4b05 ldr r3, [pc, #20] @ (59c <_init_chip+0x20>) 586: 4798 blx r3 _sysctrl_init_sources(); 588: 4b05 ldr r3, [pc, #20] @ (5a0 <_init_chip+0x24>) 58a: 4798 blx r3 #if _GCLK_INIT_1ST _gclk_init_generators_by_fref(_GCLK_INIT_1ST); #endif _sysctrl_init_referenced_generators(); 58c: 4b05 ldr r3, [pc, #20] @ (5a4 <_init_chip+0x28>) 58e: 4798 blx r3 _gclk_init_generators_by_fref(_GCLK_INIT_LAST); 590: 203f movs r0, #63 @ 0x3f 592: 4b05 ldr r3, [pc, #20] @ (5a8 <_init_chip+0x2c>) 594: 4798 blx r3 #if CONF_DMAC_ENABLE _pm_enable_bus_clock(PM_BUS_AHB, DMAC); _pm_enable_bus_clock(PM_BUS_APBB, DMAC); _dma_init(); #endif } 596: bd10 pop {r4, pc} 598: 41004000 .word 0x41004000 59c: 000005bd .word 0x000005bd 5a0: 00000529 .word 0x00000529 5a4: 0000056d .word 0x0000056d 5a8: 000005dd .word 0x000005dd 000005ac <_get_cycles_for_ms>: { switch (power) { case 8: return (ms * (freq / 100000)) * 100; case 7: return (ms * (freq / 10000)) * 10; 5ac: 23fa movs r3, #250 @ 0xfa 5ae: 009b lsls r3, r3, #2 5b0: 4358 muls r0, r3 * \brief Retrieve the amount of cycles to delay for the given amount of ms */ uint32_t _get_cycles_for_ms(const uint16_t ms) { return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); } 5b2: 4770 bx lr 000005b4 : /** * \brief Assert function */ void assert(const bool condition, const char *const file, const int line) { if (!(condition)) { 5b4: 2800 cmp r0, #0 5b6: d100 bne.n 5ba __asm("BKPT #0"); 5b8: be00 bkpt 0x0000 } (void)file; (void)line; } 5ba: 4770 bx lr 000005bc <_pm_init>: } static inline void hri_pm_set_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) { PM_CRITICAL_SECTION_ENTER(); ((Pm *)hw)->CPUSEL.reg |= PM_CPUSEL_CPUDIV(mask); 5bc: 4b06 ldr r3, [pc, #24] @ (5d8 <_pm_init+0x1c>) 5be: 7a1a ldrb r2, [r3, #8] 5c0: b2d2 uxtb r2, r2 5c2: 721a strb r2, [r3, #8] } static inline void hri_pm_set_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) { PM_CRITICAL_SECTION_ENTER(); ((Pm *)hw)->APBASEL.reg |= PM_APBASEL_APBADIV(mask); 5c4: 7a5a ldrb r2, [r3, #9] 5c6: b2d2 uxtb r2, r2 5c8: 725a strb r2, [r3, #9] } static inline void hri_pm_set_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) { PM_CRITICAL_SECTION_ENTER(); ((Pm *)hw)->APBBSEL.reg |= PM_APBBSEL_APBBDIV(mask); 5ca: 7a9a ldrb r2, [r3, #10] 5cc: b2d2 uxtb r2, r2 5ce: 729a strb r2, [r3, #10] } static inline void hri_pm_set_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) { PM_CRITICAL_SECTION_ENTER(); ((Pm *)hw)->APBCSEL.reg |= PM_APBCSEL_APBCDIV(mask); 5d0: 7ada ldrb r2, [r3, #11] 5d2: b2d2 uxtb r2, r2 5d4: 72da strb r2, [r3, #11] { hri_pm_set_CPUSEL_CPUDIV_bf(PM, CONF_CPU_DIV); hri_pm_set_APBASEL_APBADIV_bf(PM, CONF_APBA_DIV); hri_pm_set_APBBSEL_APBBDIV_bf(PM, CONF_APBB_DIV); hri_pm_set_APBCSEL_APBCDIV_bf(PM, CONF_APBC_DIV); } 5d6: 4770 bx lr 5d8: 40000400 .word 0x40000400 000005dc <_gclk_init_generators_by_fref>: void _gclk_init_generators_by_fref(uint32_t bm) { #if CONF_GCLK_GENERATOR_0_CONFIG == 1 if (bm & (1ul << 0)) { 5dc: 07c0 lsls r0, r0, #31 5de: d509 bpl.n 5f4 <_gclk_init_generators_by_fref+0x18> } static inline void hri_gclk_write_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t data) { GCLK_CRITICAL_SECTION_ENTER(); ((Gclk *)hw)->GENDIV.reg = data; 5e0: 2380 movs r3, #128 @ 0x80 5e2: 4a05 ldr r2, [pc, #20] @ (5f8 <_gclk_init_generators_by_fref+0x1c>) 5e4: 005b lsls r3, r3, #1 5e6: 6093 str r3, [r2, #8] ((Gclk *)hw)->GENCTRL.reg = data; 5e8: 2383 movs r3, #131 @ 0x83 5ea: 025b lsls r3, r3, #9 5ec: 6053 str r3, [r2, #4] while (((const Gclk *)hw)->STATUS.bit.SYNCBUSY) 5ee: 7853 ldrb r3, [r2, #1] 5f0: 09db lsrs r3, r3, #7 5f2: d1fc bne.n 5ee <_gclk_init_generators_by_fref+0x12> | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SRC | GCLK_GENCTRL_ID(5)); } #endif } 5f4: 4770 bx lr 5f6: 46c0 nop @ (mov r8, r8) 5f8: 40000c00 .word 0x40000c00 000005fc
: #include "leds.h" int main(void) { /* Initializes MCU, drivers and middleware */ atmel_start_init(); 5fc: 4b08 ldr r3, [pc, #32] @ (620 ) { 5fe: b510 push {r4, lr} atmel_start_init(); 600: 4798 blx r3 /* Application code */ int i = 1; leds_reset(); 602: 4b08 ldr r3, [pc, #32] @ (624 ) 604: 4798 blx r3 while (1) { leds_turn_on(i); leds_draw(); delay_ms(1); i>12 ? i=1 : i++; 606: 2401 movs r4, #1 leds_turn_on(i); 608: b2e0 uxtb r0, r4 60a: 4b07 ldr r3, [pc, #28] @ (628 ) 60c: 4798 blx r3 leds_draw(); 60e: 4b07 ldr r3, [pc, #28] @ (62c ) 610: 4798 blx r3 delay_ms(1); 612: 2001 movs r0, #1 614: 4b06 ldr r3, [pc, #24] @ (630 ) 616: 4798 blx r3 i>12 ? i=1 : i++; 618: 2c0d cmp r4, #13 61a: d0f4 beq.n 606 61c: 3401 adds r4, #1 61e: e7f3 b.n 608 620: 000009e5 .word 0x000009e5 624: 00000131 .word 0x00000131 628: 00000125 .word 0x00000125 62c: 000001f5 .word 0x000001f5 630: 00000509 .word 0x00000509 00000634 : * \brief Check whether element belongs to list */ bool is_list_element(const struct list_descriptor *const list, const void *const element) { struct list_element *it; for (it = list->head; it; it = it->next) { 634: 6800 ldr r0, [r0, #0] 636: 2800 cmp r0, #0 638: d100 bne.n 63c return true; } } return false; } 63a: 4770 bx lr if (it == element) { 63c: 4288 cmp r0, r1 63e: d1f9 bne.n 634 return true; 640: 2001 movs r0, #1 642: e7fa b.n 63a 00000644 : /** * \brief Insert an element as list head */ void list_insert_as_head(struct list_descriptor *const list, void *const element) { 644: b570 push {r4, r5, r6, lr} ASSERT(!is_list_element(list, element)); 646: 4b07 ldr r3, [pc, #28] @ (664 ) { 648: 000d movs r5, r1 64a: 0004 movs r4, r0 ASSERT(!is_list_element(list, element)); 64c: 4798 blx r3 64e: 2301 movs r3, #1 650: 4058 eors r0, r3 652: 2239 movs r2, #57 @ 0x39 654: 4904 ldr r1, [pc, #16] @ (668 ) 656: 4b05 ldr r3, [pc, #20] @ (66c ) 658: b2c0 uxtb r0, r0 65a: 4798 blx r3 ((struct list_element *)element)->next = list->head; 65c: 6823 ldr r3, [r4, #0] 65e: 602b str r3, [r5, #0] list->head = (struct list_element *)element; 660: 6025 str r5, [r4, #0] } 662: bd70 pop {r4, r5, r6, pc} 664: 00000635 .word 0x00000635 668: 00000bb5 .word 0x00000bb5 66c: 000005b5 .word 0x000005b5 00000670 : /** * \brief Insert an element after the given list element */ void list_insert_after(void *const after, void *const element) { ((struct list_element *)element)->next = ((struct list_element *)after)->next; 670: 6803 ldr r3, [r0, #0] 672: 600b str r3, [r1, #0] ((struct list_element *)after)->next = (struct list_element *)element; 674: 6001 str r1, [r0, #0] } 676: 4770 bx lr 00000678 : /** * \brief Removes list head */ void *list_remove_head(struct list_descriptor *const list) { 678: 0003 movs r3, r0 if (list->head) { 67a: 6800 ldr r0, [r0, #0] 67c: 2800 cmp r0, #0 67e: d001 beq.n 684 struct list_element *tmp = list->head; list->head = list->head->next; 680: 6802 ldr r2, [r0, #0] 682: 601a str r2, [r3, #0] return (void *)tmp; } return NULL; } 684: 4770 bx lr 00000686 : typedef uint8_t hri_rtcmode2_intflag_reg_t; typedef uint8_t hri_rtcmode2_mask_reg_t; static inline void hri_rtc_wait_for_sync(const void *const hw) { while (((const Rtc *)hw)->MODE0.STATUS.bit.SYNCBUSY) 686: 7a83 ldrb r3, [r0, #10] 688: 09db lsrs r3, r3, #7 68a: d1fc bne.n 686 ; } 68c: 4770 bx lr ... 00000690 <_timer_init>: /** * \brief Initialize Timer */ int32_t _timer_init(struct _timer_device *const dev, void *const hw) { 690: b5f8 push {r3, r4, r5, r6, r7, lr} 692: 0005 movs r5, r0 ASSERT(dev); 694: 1e43 subs r3, r0, #1 696: 4198 sbcs r0, r3 { 698: 000c movs r4, r1 } static inline void hri_rtcmode0_write_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t data) { RTC_CRITICAL_SECTION_ENTER(); ((Rtc *)hw)->MODE0.CTRL.reg = data; 69a: 2701 movs r7, #1 ASSERT(dev); 69c: 2230 movs r2, #48 @ 0x30 69e: 490d ldr r1, [pc, #52] @ (6d4 <_timer_init+0x44>) 6a0: 4b0d ldr r3, [pc, #52] @ (6d8 <_timer_init+0x48>) 6a2: b2c0 uxtb r0, r0 6a4: 4798 blx r3 hri_rtc_wait_for_sync(hw); 6a6: 4e0d ldr r6, [pc, #52] @ (6dc <_timer_init+0x4c>) uint16_t register_value; dev->hw = hw; 6a8: 60ec str r4, [r5, #12] 6aa: 0020 movs r0, r4 ((Rtc *)hw)->MODE0.CTRL.reg = data; 6ac: 8027 strh r7, [r4, #0] hri_rtc_wait_for_sync(hw); 6ae: 47b0 blx r6 hri_rtcmode0_write_CTRL_reg(dev->hw, RTC_MODE0_CTRL_SWRST); hri_rtcmode0_wait_for_sync(dev->hw); 6b0: 0020 movs r0, r4 6b2: 47b0 blx r6 ((Rtc *)hw)->MODE0.CTRL.reg = data; 6b4: 2380 movs r3, #128 @ 0x80 hri_rtc_wait_for_sync(hw); 6b6: 0020 movs r0, r4 ((Rtc *)hw)->MODE0.CTRL.reg = data; 6b8: 8023 strh r3, [r4, #0] hri_rtc_wait_for_sync(hw); 6ba: 47b0 blx r6 static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) { uint32_t tmp; RTC_CRITICAL_SECTION_ENTER(); tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; 6bc: 69a3 ldr r3, [r4, #24] tmp &= ~RTC_MODE0_COMP_COMP_Msk; tmp |= RTC_MODE0_COMP_COMP(data); ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; 6be: 2380 movs r3, #128 @ 0x80 6c0: 00db lsls r3, r3, #3 hri_rtc_wait_for_sync(hw); 6c2: 0020 movs r0, r4 ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; 6c4: 61a3 str r3, [r4, #24] hri_rtc_wait_for_sync(hw); 6c6: 47b0 blx r6 | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos) | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos) | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos) | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos) | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos)); #endif _rtc_dev = dev; 6c8: 4b05 ldr r3, [pc, #20] @ (6e0 <_timer_init+0x50>) return ERR_NONE; } 6ca: 2000 movs r0, #0 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; 6cc: 71e7 strb r7, [r4, #7] _rtc_dev = dev; 6ce: 601d str r5, [r3, #0] } 6d0: bdf8 pop {r3, r4, r5, r6, r7, pc} 6d2: 46c0 nop @ (mov r8, r8) 6d4: 00000bd3 .word 0x00000bd3 6d8: 000005b5 .word 0x000005b5 6dc: 00000687 .word 0x00000687 6e0: 20000030 .word 0x20000030 000006e4 <_rtc_get_timer>: * \brief Retrieve timer helper functions */ struct _timer_hpl_interface *_rtc_get_timer(void) { return NULL; } 6e4: 2000 movs r0, #0 6e6: 4770 bx lr 000006e8 : /** * \brief Rtc interrupt handler */ void RTC_Handler(void) { 6e8: b570 push {r4, r5, r6, lr} if (flag & RTC_MODE0_INTFLAG_CMP0) { 6ea: 2501 movs r5, #1 _rtc_timer_interrupt_handler(_rtc_dev); 6ec: 4b06 ldr r3, [pc, #24] @ (708 ) 6ee: 681c ldr r4, [r3, #0] uint16_t flag = hri_rtcmode0_read_INTFLAG_reg(dev->hw); 6f0: 68e3 ldr r3, [r4, #12] return ((Rtc *)hw)->MODE0.INTFLAG.reg; 6f2: 7a1b ldrb r3, [r3, #8] if (flag & RTC_MODE0_INTFLAG_CMP0) { 6f4: 422b tst r3, r5 6f6: d006 beq.n 706 if (dev->timer_cb.period_expired) { 6f8: 6823 ldr r3, [r4, #0] 6fa: 2b00 cmp r3, #0 6fc: d001 beq.n 702 dev->timer_cb.period_expired(dev); 6fe: 0020 movs r0, r4 700: 4798 blx r3 hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw); 702: 68e3 ldr r3, [r4, #12] ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; 704: 721d strb r5, [r3, #8] } 706: bd70 pop {r4, r5, r6, pc} 708: 20000030 .word 0x20000030 0000070c : ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 70c: 23c0 movs r3, #192 @ 0xc0 70e: 2210 movs r2, #16 710: 05db lsls r3, r3, #23 712: 605a str r2, [r3, #4] ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 714: 4a09 ldr r2, [pc, #36] @ (73c ) 716: 4b0a ldr r3, [pc, #40] @ (740 ) tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; 718: 0011 movs r1, r2 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 71a: 6293 str r3, [r2, #40] @ 0x28 71c: 23c0 movs r3, #192 @ 0xc0 71e: 061b lsls r3, r3, #24 720: 6293 str r3, [r2, #40] @ 0x28 tmp |= value << PORT_PINCFG_PMUXEN_Pos; 722: 2201 movs r2, #1 tmp &= ~PORT_PMUX_PMUXE_Msk; 724: 200f movs r0, #15 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; 726: 3144 adds r1, #68 @ 0x44 728: 780b ldrb r3, [r1, #0] tmp |= value << PORT_PINCFG_PMUXEN_Pos; 72a: 4313 orrs r3, r2 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; 72c: 700b strb r3, [r1, #0] tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; 72e: 4b03 ldr r3, [pc, #12] @ (73c ) 730: 3332 adds r3, #50 @ 0x32 732: 7819 ldrb r1, [r3, #0] tmp &= ~PORT_PMUX_PMUXE_Msk; 734: 4381 bics r1, r0 tmp |= PORT_PMUX_PMUXE(data); 736: 430a orrs r2, r1 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; 738: 701a strb r2, [r3, #0] // Disable digital pin circuitry gpio_set_pin_direction(PIN_ADC, GPIO_DIRECTION_OFF); gpio_set_pin_function(PIN_ADC, PINMUX_PA04B_ADC_AIN2); } 73a: 4770 bx lr 73c: 41004400 .word 0x41004400 740: 40000010 .word 0x40000010 00000744 : peripheral = (uint32_t)_pm_get_apbb_index(module); PM->APBBMASK.reg |= 1 << peripheral; } break; case PM_BUS_APBC: PM->APBCMASK.reg |= 1 << peripheral; 744: 2380 movs r3, #128 @ 0x80 746: 4a04 ldr r2, [pc, #16] @ (758 ) 748: 005b lsls r3, r3, #1 74a: 6a11 ldr r1, [r2, #32] 74c: 430b orrs r3, r1 74e: 6213 str r3, [r2, #32] ((Gclk *)hw)->CLKCTRL.reg = data; 750: 4b02 ldr r3, [pc, #8] @ (75c ) 752: 4a03 ldr r2, [pc, #12] @ (760 ) 754: 805a strh r2, [r3, #2] void ADC_0_CLOCK_init(void) { _pm_enable_bus_clock(PM_BUS_APBC, ADC); _gclk_enable_channel(ADC_GCLK_ID, CONF_GCLK_ADC_SRC); } 756: 4770 bx lr 758: 40000400 .word 0x40000400 75c: 40000c00 .word 0x40000c00 760: 00004013 .word 0x00004013 00000764 : void ADC_0_init(void) { 764: b510 push {r4, lr} ADC_0_CLOCK_init(); 766: 4b05 ldr r3, [pc, #20] @ (77c ) 768: 4798 blx r3 ADC_0_PORT_init(); 76a: 4b05 ldr r3, [pc, #20] @ (780 ) 76c: 4798 blx r3 adc_sync_init(&ADC_0, ADC, (void *)NULL); 76e: 2200 movs r2, #0 770: 4804 ldr r0, [pc, #16] @ (784 ) 772: 4905 ldr r1, [pc, #20] @ (788 ) 774: 4b05 ldr r3, [pc, #20] @ (78c ) 776: 4798 blx r3 } 778: bd10 pop {r4, pc} 77a: 46c0 nop @ (mov r8, r8) 77c: 00000745 .word 0x00000745 780: 0000070d .word 0x0000070d 784: 20000034 .word 0x20000034 788: 42002000 .word 0x42002000 78c: 000008c1 .word 0x000008c1 00000790 : 790: 4b10 ldr r3, [pc, #64] @ (7d4 ) 792: 4a11 ldr r2, [pc, #68] @ (7d8 ) void EXTERNAL_IRQ_0_init(void) { 794: b510 push {r4, lr} 796: 805a strh r2, [r3, #2] ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 798: 23c0 movs r3, #192 @ 0xc0 79a: 2280 movs r2, #128 @ 0x80 79c: 05db lsls r3, r3, #23 79e: 0212 lsls r2, r2, #8 7a0: 605a str r2, [r3, #4] ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 7a2: 4a0e ldr r2, [pc, #56] @ (7dc ) 7a4: 4b0e ldr r3, [pc, #56] @ (7e0 ) ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; 7a6: 2104 movs r1, #4 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 7a8: 6293 str r3, [r2, #40] @ 0x28 7aa: 4b0e ldr r3, [pc, #56] @ (7e4 ) 7ac: 6293 str r3, [r2, #40] @ 0x28 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; 7ae: 0013 movs r3, r2 7b0: 334f adds r3, #79 @ 0x4f 7b2: 781a ldrb r2, [r3, #0] 7b4: 438a bics r2, r1 7b6: 701a strb r2, [r3, #0] tmp |= value << PORT_PINCFG_PMUXEN_Pos; 7b8: 2201 movs r2, #1 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; 7ba: 7819 ldrb r1, [r3, #0] tmp |= value << PORT_PINCFG_PMUXEN_Pos; 7bc: 430a orrs r2, r1 tmp &= ~PORT_PMUX_PMUXO_Msk; 7be: 210f movs r1, #15 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; 7c0: 701a strb r2, [r3, #0] tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; 7c2: 4b06 ldr r3, [pc, #24] @ (7dc ) 7c4: 3337 adds r3, #55 @ 0x37 7c6: 781a ldrb r2, [r3, #0] tmp &= ~PORT_PMUX_PMUXO_Msk; 7c8: 400a ands r2, r1 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; 7ca: 701a strb r2, [r3, #0] // Pull-down GPIO_PULL_OFF); gpio_set_pin_function(PIN_BUTTON, PINMUX_PA15A_EIC_EXTINT1); ext_irq_init(); 7cc: 4b06 ldr r3, [pc, #24] @ (7e8 ) 7ce: 4798 blx r3 } 7d0: bd10 pop {r4, pc} 7d2: 46c0 nop @ (mov r8, r8) 7d4: 40000c00 .word 0x40000c00 7d8: 00004005 .word 0x00004005 7dc: 41004400 .word 0x41004400 7e0: 40028000 .word 0x40028000 7e4: c0020000 .word 0xc0020000 7e8: 00000921 .word 0x00000921 000007ec : void delay_driver_init(void) { 7ec: b510 push {r4, lr} delay_init(SysTick); 7ee: 4802 ldr r0, [pc, #8] @ (7f8 ) 7f0: 4b02 ldr r3, [pc, #8] @ (7fc ) 7f2: 4798 blx r3 } 7f4: bd10 pop {r4, pc} 7f6: 46c0 nop @ (mov r8, r8) 7f8: e000e010 .word 0xe000e010 7fc: 000004f5 .word 0x000004f5 00000800 : PM->APBAMASK.reg |= 1 << peripheral; 800: 2310 movs r3, #16 802: 4a04 ldr r2, [pc, #16] @ (814 ) 804: 6991 ldr r1, [r2, #24] 806: 430b orrs r3, r1 808: 6193 str r3, [r2, #24] 80a: 4b03 ldr r3, [pc, #12] @ (818 ) 80c: 4a03 ldr r2, [pc, #12] @ (81c ) 80e: 805a strh r2, [r3, #2] void WDT_0_CLOCK_init(void) { _pm_enable_bus_clock(PM_BUS_APBA, WDT); _gclk_enable_channel(WDT_GCLK_ID, CONF_GCLK_WDT_SRC); } 810: 4770 bx lr 812: 46c0 nop @ (mov r8, r8) 814: 40000400 .word 0x40000400 818: 40000c00 .word 0x40000c00 81c: 00004003 .word 0x00004003 00000820 : void WDT_0_init(void) { 820: b510 push {r4, lr} WDT_0_CLOCK_init(); 822: 4b07 ldr r3, [pc, #28] @ (840 ) 824: 4798 blx r3 * \retval 0 Completed sucessfully. * \retval -1 Always on or enabled, don't need init again. */ static inline int32_t wdt_init(struct wdt_descriptor *const wdt, const void *hw) { ASSERT(wdt && hw); 826: 2248 movs r2, #72 @ 0x48 828: 2001 movs r0, #1 82a: 4906 ldr r1, [pc, #24] @ (844 ) 82c: 4b06 ldr r3, [pc, #24] @ (848 ) 82e: 4798 blx r3 wdt->dev.hw = (void *)hw; 830: 4806 ldr r0, [pc, #24] @ (84c ) 832: 4b07 ldr r3, [pc, #28] @ (850 ) return _wdt_init(&wdt->dev); 834: 3004 adds r0, #4 wdt->dev.hw = (void *)hw; 836: 6003 str r3, [r0, #0] return _wdt_init(&wdt->dev); 838: 4b06 ldr r3, [pc, #24] @ (854 ) 83a: 4798 blx r3 wdt_init(&WDT_0, WDT); } 83c: bd10 pop {r4, pc} 83e: 46c0 nop @ (mov r8, r8) 840: 00000801 .word 0x00000801 844: 00000be8 .word 0x00000be8 848: 000005b5 .word 0x000005b5 84c: 20000034 .word 0x20000034 850: 40001000 .word 0x40001000 854: 00000285 .word 0x00000285 00000858 : void system_init(void) { 858: b510 push {r4, lr} * Currently the following initialization functions are supported: * - System clock initialization */ static inline void init_mcu(void) { _init_chip(); 85a: 4b0d ldr r3, [pc, #52] @ (890 ) 85c: 4798 blx r3 init_mcu(); ADC_0_init(); 85e: 4b0d ldr r3, [pc, #52] @ (894 ) 860: 4798 blx r3 EXTERNAL_IRQ_0_init(); 862: 4b0d ldr r3, [pc, #52] @ (898 ) 864: 4798 blx r3 delay_driver_init(); 866: 4b0d ldr r3, [pc, #52] @ (89c ) 868: 4798 blx r3 86a: 2320 movs r3, #32 86c: 4a0c ldr r2, [pc, #48] @ (8a0 ) 86e: 6991 ldr r1, [r2, #24] 870: 430b orrs r3, r1 872: 6193 str r3, [r2, #24] 874: 4a0b ldr r2, [pc, #44] @ (8a4 ) 876: 4b0c ldr r3, [pc, #48] @ (8a8 ) 878: 805a strh r2, [r3, #2] timer_init(&TIMER_0, RTC, _rtc_get_timer()); 87a: 4b0c ldr r3, [pc, #48] @ (8ac ) 87c: 4798 blx r3 87e: 4b0c ldr r3, [pc, #48] @ (8b0 ) 880: 0002 movs r2, r0 882: 490c ldr r1, [pc, #48] @ (8b4 ) 884: 0018 movs r0, r3 886: 4b0c ldr r3, [pc, #48] @ (8b8 ) 888: 4798 blx r3 TIMER_0_init(); WDT_0_init(); 88a: 4b0c ldr r3, [pc, #48] @ (8bc ) 88c: 4798 blx r3 } 88e: bd10 pop {r4, pc} 890: 0000057d .word 0x0000057d 894: 00000765 .word 0x00000765 898: 00000791 .word 0x00000791 89c: 000007ed .word 0x000007ed 8a0: 40000400 .word 0x40000400 8a4: 00004004 .word 0x00004004 8a8: 40000c00 .word 0x40000c00 8ac: 000006e5 .word 0x000006e5 8b0: 2000003c .word 0x2000003c 8b4: 40001400 .word 0x40001400 8b8: 000004b9 .word 0x000004b9 8bc: 00000821 .word 0x00000821 000008c0 : /** * \brief Initialize ADC */ int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func) { 8c0: b570 push {r4, r5, r6, lr} 8c2: 000d movs r5, r1 ASSERT(descr && hw); 8c4: 002b movs r3, r5 { 8c6: 0004 movs r4, r0 ASSERT(descr && hw); 8c8: 1e5a subs r2, r3, #1 8ca: 4193 sbcs r3, r2 8cc: 1e42 subs r2, r0, #1 8ce: 4190 sbcs r0, r2 8d0: 4904 ldr r1, [pc, #16] @ (8e4 ) 8d2: 2239 movs r2, #57 @ 0x39 8d4: 4018 ands r0, r3 8d6: 4b04 ldr r3, [pc, #16] @ (8e8 ) 8d8: 4798 blx r3 return _adc_sync_init(&descr->device, hw); 8da: 0029 movs r1, r5 8dc: 0020 movs r0, r4 8de: 4b03 ldr r3, [pc, #12] @ (8ec ) 8e0: 4798 blx r3 } 8e2: bd70 pop {r4, r5, r6, pc} 8e4: 00000c01 .word 0x00000c01 8e8: 000005b5 .word 0x000005b5 8ec: 00000a99 .word 0x00000a99 000008f0 : * * \param[in] pin The pin which triggered the interrupt */ static void process_ext_irq(const uint32_t pin) { uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; 8f0: 2201 movs r2, #1 { 8f2: b570 push {r4, r5, r6, lr} } return; } if (ext_irqs[middle].pin < pin) { lower = middle + 1; 8f4: 0015 movs r5, r2 if (ext_irqs[middle].pin == pin) { 8f6: 4c09 ldr r4, [pc, #36] @ (91c ) 8f8: 6861 ldr r1, [r4, #4] uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; 8fa: 2300 movs r3, #0 middle = (upper + lower) >> 1; 8fc: 18d3 adds r3, r2, r3 8fe: 105b asrs r3, r3, #1 if (middle >= EXT_IRQ_AMOUNT) { 900: d105 bne.n 90e if (ext_irqs[middle].pin == pin) { 902: 4281 cmp r1, r0 904: d104 bne.n 910 if (ext_irqs[middle].cb) { 906: 6823 ldr r3, [r4, #0] 908: 2b00 cmp r3, #0 90a: d000 beq.n 90e ext_irqs[middle].cb(); 90c: 4798 blx r3 } else { upper = middle - 1; } } } 90e: bd70 pop {r4, r5, r6, pc} lower = middle + 1; 910: 002b movs r3, r5 if (ext_irqs[middle].pin < pin) { 912: 4281 cmp r1, r0 914: d3f2 bcc.n 8fc upper = middle - 1; 916: 22ff movs r2, #255 @ 0xff 918: e7ef b.n 8fa 91a: 46c0 nop @ (mov r8, r8) 91c: 20000058 .word 0x20000058 00000920 : ext_irqs[i].pin = 0xFFFFFFFF; 920: 2201 movs r2, #1 922: 4b05 ldr r3, [pc, #20] @ (938 ) 924: 4252 negs r2, r2 { 926: b510 push {r4, lr} ext_irqs[i].pin = 0xFFFFFFFF; 928: 605a str r2, [r3, #4] ext_irqs[i].cb = NULL; 92a: 2200 movs r2, #0 92c: 601a str r2, [r3, #0] return _ext_irq_init(process_ext_irq); 92e: 4803 ldr r0, [pc, #12] @ (93c ) 930: 4b03 ldr r3, [pc, #12] @ (940 ) 932: 4798 blx r3 } 934: bd10 pop {r4, pc} 936: 46c0 nop @ (mov r8, r8) 938: 20000058 .word 0x20000058 93c: 000008f1 .word 0x000008f1 940: 000002dd .word 0x000002dd 00000944 : /** * \brief Default interrupt handler for unused IRQs. */ void Dummy_Handler(void) { while (1) { 944: e7fe b.n 944 ... 00000948 : if (pSrc != pDest) { 948: 4a1a ldr r2, [pc, #104] @ (9b4 ) 94a: 4b1b ldr r3, [pc, #108] @ (9b8 ) { 94c: b510 push {r4, lr} for (; pDest < &_erelocate;) { 94e: 491b ldr r1, [pc, #108] @ (9bc ) if (pSrc != pDest) { 950: 429a cmp r2, r3 952: d12a bne.n 9aa *pDest++ = 0; 954: 2100 movs r1, #0 956: 4b1a ldr r3, [pc, #104] @ (9c0 ) for (pDest = &_szero; pDest < &_ezero;) { 958: 4a1a ldr r2, [pc, #104] @ (9c4 ) 95a: 4293 cmp r3, r2 95c: d328 bcc.n 9b0 SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); 95e: 22ff movs r2, #255 @ 0xff 960: 4b19 ldr r3, [pc, #100] @ (9c8 ) DMAC->QOSCTRL.bit.DQOS = 2; 962: 2130 movs r1, #48 @ 0x30 SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); 964: 4393 bics r3, r2 966: 4a19 ldr r2, [pc, #100] @ (9cc ) 968: 6093 str r3, [r2, #8] SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; 96a: 2202 movs r2, #2 96c: 4b18 ldr r3, [pc, #96] @ (9d0 ) 96e: 625a str r2, [r3, #36] @ 0x24 DMAC->QOSCTRL.bit.DQOS = 2; 970: 4b18 ldr r3, [pc, #96] @ (9d4 ) 972: 7b98 ldrb r0, [r3, #14] 974: 4388 bics r0, r1 976: 3910 subs r1, #16 978: 4301 orrs r1, r0 97a: 7399 strb r1, [r3, #14] DMAC->QOSCTRL.bit.FQOS = 2; 97c: 210c movs r1, #12 97e: 7b98 ldrb r0, [r3, #14] 980: 4388 bics r0, r1 982: 3904 subs r1, #4 984: 4301 orrs r1, r0 DMAC->QOSCTRL.bit.WRBQOS = 2; 986: 2003 movs r0, #3 DMAC->QOSCTRL.bit.FQOS = 2; 988: 7399 strb r1, [r3, #14] DMAC->QOSCTRL.bit.WRBQOS = 2; 98a: 7b99 ldrb r1, [r3, #14] 98c: 4381 bics r1, r0 98e: 430a orrs r2, r1 990: 739a strb r2, [r3, #14] NVMCTRL->CTRLB.bit.MANW = 1; 992: 2380 movs r3, #128 @ 0x80 994: 4a10 ldr r2, [pc, #64] @ (9d8 ) 996: 6851 ldr r1, [r2, #4] 998: 430b orrs r3, r1 99a: 6053 str r3, [r2, #4] __libc_init_array(); 99c: 4b0f ldr r3, [pc, #60] @ (9dc ) 99e: 4798 blx r3 main(); 9a0: 4b0f ldr r3, [pc, #60] @ (9e0 ) 9a2: 4798 blx r3 while (1) 9a4: e7fe b.n 9a4 *pDest++ = *pSrc++; 9a6: ca01 ldmia r2!, {r0} 9a8: c301 stmia r3!, {r0} for (; pDest < &_erelocate;) { 9aa: 428b cmp r3, r1 9ac: d3fb bcc.n 9a6 9ae: e7d1 b.n 954 *pDest++ = 0; 9b0: c302 stmia r3!, {r1} 9b2: e7d2 b.n 95a 9b4: 00000c58 .word 0x00000c58 9b8: 20000000 .word 0x20000000 9bc: 20000000 .word 0x20000000 9c0: 20000000 .word 0x20000000 9c4: 20000060 .word 0x20000060 9c8: 00000000 .word 0x00000000 9cc: e000ed00 .word 0xe000ed00 9d0: 410070fc .word 0x410070fc 9d4: 41004800 .word 0x41004800 9d8: 41004000 .word 0x41004000 9dc: 00000b15 .word 0x00000b15 9e0: 000005fd .word 0x000005fd 000009e4 : /** * Initializes MCU, drivers and middleware in the project **/ void atmel_start_init(void) { 9e4: b510 push {r4, lr} system_init(); 9e6: 4b01 ldr r3, [pc, #4] @ (9ec ) 9e8: 4798 blx r3 } 9ea: bd10 pop {r4, pc} 9ec: 00000859 .word 0x00000859 000009f0 : typedef uint8_t hri_adc_swtrig_reg_t; typedef uint8_t hri_adc_winctrl_reg_t; static inline void hri_adc_wait_for_sync(const void *const hw) { while (((const Adc *)hw)->STATUS.bit.SYNCBUSY) 9f0: 7e43 ldrb r3, [r0, #25] 9f2: 09db lsrs r3, r3, #7 9f4: d1fc bne.n 9f0 ; } 9f6: 4770 bx lr 000009f8 <_adc_init.constprop.0.isra.0>: * \brief Initialize ADC * * \param[in] hw The pointer to hardware instance * \param[in] i The number of hardware instance */ static int32_t _adc_init(void *const hw, const uint8_t i) 9f8: b5f8 push {r3, r4, r5, r6, r7, lr} { ASSERT(hw == ADC); 9fa: 4b21 ldr r3, [pc, #132] @ (a80 <_adc_init.constprop.0.isra.0+0x88>) static int32_t _adc_init(void *const hw, const uint8_t i) 9fc: 0004 movs r4, r0 ASSERT(hw == ADC); 9fe: 18c0 adds r0, r0, r3 a00: 4243 negs r3, r0 a02: 4158 adcs r0, r3 a04: 2294 movs r2, #148 @ 0x94 a06: 491f ldr r1, [pc, #124] @ (a84 <_adc_init.constprop.0.isra.0+0x8c>) a08: 4b1f ldr r3, [pc, #124] @ (a88 <_adc_init.constprop.0.isra.0+0x90>) a0a: b2c0 uxtb r0, r0 a0c: 4798 blx r3 uint16_t calib_reg; calib_reg = ADC_CALIB_BIAS_CAL((*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)) a0e: 22e0 movs r2, #224 @ 0xe0 a10: 4b1e ldr r3, [pc, #120] @ (a8c <_adc_init.constprop.0.isra.0+0x94>) a12: 00d2 lsls r2, r2, #3 a14: 681b ldr r3, [r3, #0] | ADC_CALIB_LINEARITY_CAL((*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)); hri_adc_wait_for_sync(hw); a16: 0020 movs r0, r4 calib_reg = ADC_CALIB_BIAS_CAL((*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)) a18: 015d lsls r5, r3, #5 a1a: 4015 ands r5, r2 | ADC_CALIB_LINEARITY_CAL((*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)); a1c: 015a lsls r2, r3, #5 a1e: 4b1c ldr r3, [pc, #112] @ (a90 <_adc_init.constprop.0.isra.0+0x98>) hri_adc_wait_for_sync(hw); a20: 4e1c ldr r6, [pc, #112] @ (a94 <_adc_init.constprop.0.isra.0+0x9c>) | ADC_CALIB_LINEARITY_CAL((*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)); a22: 681b ldr r3, [r3, #0] a24: 0edb lsrs r3, r3, #27 a26: 4313 orrs r3, r2 a28: b2db uxtb r3, r3 calib_reg = ADC_CALIB_BIAS_CAL((*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)) a2a: 431d orrs r5, r3 hri_adc_wait_for_sync(hw); a2c: 47b0 blx r6 } static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) { uint8_t tmp; tmp = ((Adc *)hw)->CTRLA.reg; a2e: 7823 ldrb r3, [r4, #0] if (hri_adc_get_CTRLA_reg(hw, ADC_CTRLA_ENABLE)) { a30: 079b lsls r3, r3, #30 a32: d503 bpl.n a3c <_adc_init.constprop.0.isra.0+0x44> } static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) { ADC_CRITICAL_SECTION_ENTER(); ((Adc *)hw)->CTRLA.reg = data; a34: 2300 movs r3, #0 hri_adc_write_CTRLA_reg(hw, 0); hri_adc_wait_for_sync(hw); a36: 0020 movs r0, r4 a38: 7023 strb r3, [r4, #0] a3a: 47b0 blx r6 a3c: 2301 movs r3, #1 } hri_adc_write_CTRLA_reg(hw, ADC_CTRLA_SWRST); hri_adc_wait_for_sync(hw); a3e: 0020 movs r0, r4 a40: 7023 strb r3, [r4, #0] a42: 47b0 blx r6 } static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) { ADC_CRITICAL_SECTION_ENTER(); ((Adc *)hw)->DBGCTRL.reg = data; a44: 0023 movs r3, r4 ((Adc *)hw)->CALIB.reg = data; a46: 8525 strh r5, [r4, #40] @ 0x28 ((Adc *)hw)->REFCTRL.reg = data; a48: 2702 movs r7, #2 ((Adc *)hw)->AVGCTRL.reg = data; a4a: 2500 movs r5, #0 ((Adc *)hw)->DBGCTRL.reg = data; a4c: 332a adds r3, #42 @ 0x2a ((Adc *)hw)->REFCTRL.reg = data; a4e: 7067 strb r7, [r4, #1] hri_adc_wait_for_sync(hw); a50: 0020 movs r0, r4 ((Adc *)hw)->AVGCTRL.reg = data; a52: 70a5 strb r5, [r4, #2] ((Adc *)hw)->SAMPCTRL.reg = data; a54: 70e5 strb r5, [r4, #3] ((Adc *)hw)->EVCTRL.reg = data; a56: 7525 strb r5, [r4, #20] ((Adc *)hw)->GAINCORR.reg = data; a58: 84a5 strh r5, [r4, #36] @ 0x24 ((Adc *)hw)->OFFSETCORR.reg = data; a5a: 84e5 strh r5, [r4, #38] @ 0x26 ((Adc *)hw)->DBGCTRL.reg = data; a5c: 701d strb r5, [r3, #0] ((Adc *)hw)->CTRLB.reg = data; a5e: 80a5 strh r5, [r4, #4] hri_adc_wait_for_sync(hw); a60: 47b0 blx r6 hri_adc_wait_for_sync(hw); a62: 0020 movs r0, r4 ((Adc *)hw)->INPUTCTRL.reg = data; a64: 6125 str r5, [r4, #16] hri_adc_wait_for_sync(hw); a66: 47b0 blx r6 hri_adc_wait_for_sync(hw); a68: 0020 movs r0, r4 ((Adc *)hw)->WINCTRL.reg = data; a6a: 7225 strb r5, [r4, #8] hri_adc_wait_for_sync(hw); a6c: 47b0 blx r6 hri_adc_wait_for_sync(hw); a6e: 0020 movs r0, r4 ((Adc *)hw)->WINLT.reg = data; a70: 83a5 strh r5, [r4, #28] hri_adc_wait_for_sync(hw); a72: 47b0 blx r6 ((Adc *)hw)->WINUT.reg = data; a74: 8425 strh r5, [r4, #32] hri_adc_wait_for_sync(hw); a76: 0020 movs r0, r4 a78: 47b0 blx r6 ((Adc *)hw)->CTRLA.reg = data; a7a: 7027 strb r7, [r4, #0] hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt); hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut); hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a); return ERR_NONE; } a7c: bdf8 pop {r3, r4, r5, r6, r7, pc} a7e: 46c0 nop @ (mov r8, r8) a80: bdffe000 .word 0xbdffe000 a84: 00000c1b .word 0x00000c1b a88: 000005b5 .word 0x000005b5 a8c: 00806024 .word 0x00806024 a90: 00806020 .word 0x00806020 a94: 000009f1 .word 0x000009f1 00000a98 <_adc_sync_init>: /** * \brief Initialize ADC */ int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw) { a98: b570 push {r4, r5, r6, lr} a9a: 0005 movs r5, r0 ASSERT(device); a9c: 1e43 subs r3, r0, #1 a9e: 4198 sbcs r0, r3 { aa0: 000c movs r4, r1 ASSERT(device); aa2: 22c5 movs r2, #197 @ 0xc5 aa4: 4904 ldr r1, [pc, #16] @ (ab8 <_adc_sync_init+0x20>) aa6: 4b05 ldr r3, [pc, #20] @ (abc <_adc_sync_init+0x24>) aa8: b2c0 uxtb r0, r0 aaa: 4798 blx r3 device->hw = hw; return _adc_init(hw, _adc_get_regs((uint32_t)hw)); aac: 0020 movs r0, r4 device->hw = hw; aae: 602c str r4, [r5, #0] return _adc_init(hw, _adc_get_regs((uint32_t)hw)); ab0: 4b03 ldr r3, [pc, #12] @ (ac0 <_adc_sync_init+0x28>) ab2: 4798 blx r3 } ab4: 2000 movs r0, #0 ab6: bd70 pop {r4, r5, r6, pc} ab8: 00000c1b .word 0x00000c1b abc: 000005b5 .word 0x000005b5 ac0: 000009f9 .word 0x000009f9 00000ac4 <__ffssi2>: ac4: b510 push {r4, lr} ac6: 2800 cmp r0, #0 ac8: d002 beq.n ad0 <__ffssi2+0xc> aca: f000 f803 bl ad4 <__ctzsi2> ace: 3001 adds r0, #1 ad0: bd10 pop {r4, pc} ad2: 46c0 nop @ (mov r8, r8) 00000ad4 <__ctzsi2>: ad4: 4241 negs r1, r0 ad6: 4008 ands r0, r1 ad8: 211c movs r1, #28 ada: 2301 movs r3, #1 adc: 041b lsls r3, r3, #16 ade: 4298 cmp r0, r3 ae0: d301 bcc.n ae6 <__ctzsi2+0x12> ae2: 0c00 lsrs r0, r0, #16 ae4: 3910 subs r1, #16 ae6: 0a1b lsrs r3, r3, #8 ae8: 4298 cmp r0, r3 aea: d301 bcc.n af0 <__ctzsi2+0x1c> aec: 0a00 lsrs r0, r0, #8 aee: 3908 subs r1, #8 af0: 091b lsrs r3, r3, #4 af2: 4298 cmp r0, r3 af4: d301 bcc.n afa <__ctzsi2+0x26> af6: 0900 lsrs r0, r0, #4 af8: 3904 subs r1, #4 afa: a202 add r2, pc, #8 @ (adr r2, b04 <__ctzsi2+0x30>) afc: 5c10 ldrb r0, [r2, r0] afe: 1a40 subs r0, r0, r1 b00: 4770 bx lr b02: 46c0 nop @ (mov r8, r8) b04: 1d1d1c1b .word 0x1d1d1c1b b08: 1e1e1e1e .word 0x1e1e1e1e b0c: 1f1f1f1f .word 0x1f1f1f1f b10: 1f1f1f1f .word 0x1f1f1f1f 00000b14 <__libc_init_array>: b14: b570 push {r4, r5, r6, lr} b16: 2600 movs r6, #0 b18: 4c0c ldr r4, [pc, #48] @ (b4c <__libc_init_array+0x38>) b1a: 4d0d ldr r5, [pc, #52] @ (b50 <__libc_init_array+0x3c>) b1c: 1b64 subs r4, r4, r5 b1e: 10a4 asrs r4, r4, #2 b20: 42a6 cmp r6, r4 b22: d109 bne.n b38 <__libc_init_array+0x24> b24: 2600 movs r6, #0 b26: f000 f887 bl c38 <_init> b2a: 4c0a ldr r4, [pc, #40] @ (b54 <__libc_init_array+0x40>) b2c: 4d0a ldr r5, [pc, #40] @ (b58 <__libc_init_array+0x44>) b2e: 1b64 subs r4, r4, r5 b30: 10a4 asrs r4, r4, #2 b32: 42a6 cmp r6, r4 b34: d105 bne.n b42 <__libc_init_array+0x2e> b36: bd70 pop {r4, r5, r6, pc} b38: 00b3 lsls r3, r6, #2 b3a: 58eb ldr r3, [r5, r3] b3c: 4798 blx r3 b3e: 3601 adds r6, #1 b40: e7ee b.n b20 <__libc_init_array+0xc> b42: 00b3 lsls r3, r6, #2 b44: 58eb ldr r3, [r5, r3] b46: 4798 blx r3 b48: 3601 adds r6, #1 b4a: e7f2 b.n b32 <__libc_init_array+0x1e> b4c: 00000c44 .word 0x00000c44 b50: 00000c44 .word 0x00000c44 b54: 00000c48 .word 0x00000c48 b58: 00000c44 .word 0x00000c44 00000b5c : b5c: 05090905 0e05050e 090e0e09 08090908 ................ b6c: 0e08080e 08050508 682f2e2e 772f6c70 ........../hpl/w b7c: 682f7464 775f6c70 632e7464 2f2e2e00 dt/hpl_wdt.c.../ b8c: 2f6c7068 2f636965 5f6c7068 2e636965 hpl/eic/hpl_eic. b9c: 2e2e0063 6c61682f 6372732f 6c61682f c.../hal/src/hal bac: 6d69745f 632e7265 2f2e2e00 2f6c6168 _timer.c.../hal/ bbc: 6c697475 72732f73 74752f63 5f736c69 utils/src/utils_ bcc: 7473696c 2e00632e 70682f2e 74722f6c list.c.../hpl/rt bdc: 70682f63 74725f6c 00632e63 682f2e2e c/hpl_rtc.c.../h bec: 692f6c61 756c636e 682f6564 775f6c61 al/include/hal_w bfc: 682e7464 2f2e2e00 2f6c6168 2f637273 dt.h.../hal/src/ c0c: 5f6c6168 5f636461 636e7973 2e00632e hal_adc_sync.c.. c1c: 70682f2e 64612f6c 70682f63 64615f6c ./hpl/adc/hpl_ad c2c: 00632e63 c.c. 00000c30 <_map>: c30: 00000001 0000000f ........ 00000c38 <_init>: c38: b5f8 push {r3, r4, r5, r6, r7, lr} c3a: 46c0 nop @ (mov r8, r8) c3c: bcf8 pop {r3, r4, r5, r6, r7} c3e: bc08 pop {r3} c40: 469e mov lr, r3 c42: 4770 bx lr 00000c44 <__frame_dummy_init_array_entry>: c44: 0101 0000 .... 00000c48 <_fini>: c48: b5f8 push {r3, r4, r5, r6, r7, lr} c4a: 46c0 nop @ (mov r8, r8) c4c: bcf8 pop {r3, r4, r5, r6, r7} c4e: bc08 pop {r3} c50: 469e mov lr, r3 c52: 4770 bx lr 00000c54 <__do_global_dtors_aux_fini_array_entry>: c54: 00d5 0000 ....