286 lines
7.2 KiB
C
286 lines
7.2 KiB
C
/**
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* \file
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*
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* \brief SAM Watchdog
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <compiler.h>
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#include <hpl_wdt.h>
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#include <hpl_wdt_base.h>
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#include <hpl_wdt_config.h>
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#include <utils_assert.h>
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/**
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* \brief Macro is used to indicate the actual clock cycles of PER which
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* SAMD21/SAMR21 supports
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*/
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/** 8 clock cycles */
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#define WDT_CLK_8CYCLE 8
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/** 16 clock cycles */
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#define WDT_CLK_16CYCLE 16
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/** 32 clock cycles */
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#define WDT_CLK_32CYCLE 32
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/** 64 clock cycles */
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#define WDT_CLK_64CYCLE 64
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/** 128 clock cycles */
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#define WDT_CLK_128CYCLE 128
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/** 256 clock cycles */
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#define WDT_CLK_256CYCLE 256
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/** 512 clock cycles */
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#define WDT_CLK_512CYCLE 512
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/** 1024 clock cycles */
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#define WDT_CLK_1024CYCLE 1024
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/** 20488 clock cycles */
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#define WDT_CLK_2048CYCLE 2048
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/** 4096 clock cycles */
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#define WDT_CLK_4096CYCLE 4096
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/** 8192 clock cycles */
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#define WDT_CLK_8192CYCLE 8192
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/** 16384 clock cycles */
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#define WDT_CLK_16384CYCLE 16384
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/**
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* \brief Macro is used to indicate the rate of second/millisecond
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*/
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#define WDT_PERIOD_RATE 1000
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/**
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* \brief WDT initialization function
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*/
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int32_t _wdt_init(struct wdt_dev *const dev)
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{
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/* Sanity check arguments */
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ASSERT(dev && dev->hw);
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if (hri_wdt_get_CTRL_ALWAYSON_bit(dev->hw) || hri_wdt_get_CTRL_ENABLE_bit(dev->hw)) {
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return ERR_DENIED;
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} else {
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if (CONF_WDT_WINDOW_EN) {
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hri_wdt_write_CONFIG_WINDOW_bf(dev->hw, CONF_WDT_WINDOW);
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} else {
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hri_wdt_clear_CTRL_WEN_bit(dev->hw);
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}
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hri_wdt_write_CONFIG_PER_bf(dev->hw, CONF_WDT_PER);
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}
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return ERR_NONE;
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}
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/**
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* \brief De-initialize WDT
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*/
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int32_t _wdt_deinit(struct wdt_dev *const dev)
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{
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/* Sanity check arguments */
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ASSERT(dev && dev->hw);
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if (hri_wdt_get_CTRL_ALWAYSON_bit(dev->hw)) {
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return ERR_DENIED;
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} else {
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hri_wdt_clear_CTRL_ENABLE_bit(dev->hw);
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}
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return ERR_NONE;
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}
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/**
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* \brief set timeout period for WDT instance
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*/
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int32_t _wdt_set_timeout_period(struct wdt_dev *const dev, const uint32_t clk_rate, const uint16_t timeout_period)
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{
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uint64_t tmp;
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uint32_t period_cycles;
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enum wdt_period_reg timeout_period_reg;
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/* Sanity check arguments */
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ASSERT(dev && dev->hw);
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if (hri_wdt_get_CTRL_ALWAYSON_bit(dev->hw) || hri_wdt_get_CTRL_ENABLE_bit(dev->hw)) {
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return ERR_DENIED;
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} else {
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/* calc the period cycles corresponding to timeout period */
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tmp = (uint64_t)timeout_period * clk_rate;
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/* check whether overflow*/
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if (tmp >> 32) {
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return ERR_INVALID_ARG;
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}
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period_cycles = (uint32_t)tmp;
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/* calc the register value corresponding to period cysles */
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switch (period_cycles) {
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case WDT_CLK_8CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_8CYCLE;
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break;
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case WDT_CLK_16CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_16CYCLE;
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break;
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case WDT_CLK_32CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_32CYCLE;
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break;
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case WDT_CLK_64CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_64CYCLE;
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break;
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case WDT_CLK_128CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_128CYCLE;
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break;
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case WDT_CLK_256CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_256CYCLE;
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break;
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case WDT_CLK_512CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_512CYCLE;
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break;
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case WDT_CLK_1024CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_1024CYCLE;
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break;
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case WDT_CLK_2048CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_2048CYCLE;
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break;
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case WDT_CLK_4096CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_4096CYCLE;
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break;
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case WDT_CLK_8192CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_8192CYCLE;
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break;
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case WDT_CLK_16384CYCLE *WDT_PERIOD_RATE:
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timeout_period_reg = WDT_PERIOD_16384CYCLE;
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break;
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default:
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return ERR_INVALID_ARG;
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}
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}
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hri_wdt_write_CONFIG_PER_bf(dev->hw, (uint8_t)timeout_period_reg);
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return ERR_NONE;
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}
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/**
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* \brief get timeout period for WDT instance
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*/
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uint32_t _wdt_get_timeout_period(const struct wdt_dev *const dev, const uint32_t clk_rate)
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{
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uint32_t period_cycles;
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uint32_t timeout_period;
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uint8_t timeout_period_reg;
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/* Sanity check arguments */
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ASSERT(dev && dev->hw);
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/* get the register value */
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timeout_period_reg = hri_wdt_read_CONFIG_PER_bf(dev->hw);
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/* convert register value to period cycles(clock cycles) */
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switch (timeout_period_reg) {
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case WDT_PERIOD_8CYCLE:
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period_cycles = WDT_CLK_8CYCLE;
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break;
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case WDT_PERIOD_16CYCLE:
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period_cycles = WDT_CLK_16CYCLE;
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break;
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case WDT_PERIOD_32CYCLE:
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period_cycles = WDT_CLK_32CYCLE;
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break;
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case WDT_PERIOD_64CYCLE:
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period_cycles = WDT_CLK_64CYCLE;
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break;
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case WDT_PERIOD_128CYCLE:
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period_cycles = WDT_CLK_128CYCLE;
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break;
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case WDT_PERIOD_256CYCLE:
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period_cycles = WDT_CLK_256CYCLE;
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break;
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case WDT_PERIOD_512CYCLE:
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period_cycles = WDT_CLK_512CYCLE;
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break;
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case WDT_PERIOD_1024CYCLE:
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period_cycles = WDT_CLK_1024CYCLE;
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break;
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case WDT_PERIOD_2048CYCLE:
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period_cycles = WDT_CLK_2048CYCLE;
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break;
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case WDT_PERIOD_4096CYCLE:
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period_cycles = WDT_CLK_4096CYCLE;
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break;
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case WDT_PERIOD_8192CYCLE:
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period_cycles = WDT_CLK_8192CYCLE;
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break;
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case WDT_PERIOD_16384CYCLE:
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period_cycles = WDT_CLK_16384CYCLE;
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break;
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default:
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return (uint32_t)-1;
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}
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/* convert period cycles(clock cycles) to timeout period(ms) */
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timeout_period = period_cycles * 1000 / clk_rate;
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return timeout_period;
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}
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/**
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* \brief enbale watchdog timer
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*/
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int32_t _wdt_enable(struct wdt_dev *const dev)
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{
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/* Sanity check arguments */
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ASSERT(dev && dev->hw);
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hri_wdt_set_CTRL_ENABLE_bit(dev->hw);
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return ERR_NONE;
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}
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/**
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* \brief disable watchdog timer
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*/
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int32_t _wdt_disable(struct wdt_dev *const dev)
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{
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/* Sanity check arguments */
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ASSERT(dev && dev->hw);
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if (hri_wdt_get_CTRL_ALWAYSON_bit(dev->hw)) {
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return ERR_DENIED;
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} else {
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hri_wdt_clear_CTRL_ENABLE_bit(dev->hw);
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}
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return ERR_NONE;
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}
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/**
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* \brief reset watchdog timer to make wdt work from start
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*/
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int32_t _wdt_feed(struct wdt_dev *const dev)
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{
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/* Sanity check arguments */
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ASSERT(dev && dev->hw);
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hri_wdt_write_CLEAR_reg(dev->hw, WDT_CLEAR_CLEAR_KEY);
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return ERR_NONE;
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}
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