qbe/amd64/targ.c
Roland Paterson-Jones 5c1eb24e2c If-conversion RFC 4 - x86 only (for now), use cmovXX
Replacement of tiny conditional jump graphlets with
conditional move instructions.

Currently enabled only for x86. Arm64 support using cselXX
will be essentially identical.

Adds (internal) frontend sel0/sel1 ops with flag-specific
backend xselXX following jnz implementation pattern.

Testing: standard QBE, cproc, harec, hare, roland
2026-01-13 18:11:30 +01:00

48 lines
851 B
C

#include "all.h"
Amd64Op amd64_op[NOp] = {
#define O(op, t, x) [O##op] =
#define X(nm, zf, lf) { nm, zf, lf, },
#include "../ops.h"
};
static int
amd64_memargs(int op)
{
return amd64_op[op].nmem;
}
#define AMD64_COMMON \
.gpr0 = RAX, \
.ngpr = NGPR, \
.fpr0 = XMM0, \
.nfpr = NFPR, \
.rglob = BIT(RBP) | BIT(RSP), \
.nrglob = 2, \
.rsave = amd64_sysv_rsave, \
.nrsave = {NGPS, NFPS}, \
.retregs = amd64_sysv_retregs, \
.argregs = amd64_sysv_argregs, \
.memargs = amd64_memargs, \
.abi0 = elimsb, \
.abi1 = amd64_sysv_abi, \
.isel = amd64_isel, \
.emitfn = amd64_emitfn, \
.cansel = 1, \
Target T_amd64_sysv = {
.name = "amd64_sysv",
.emitfin = elf_emitfin,
.asloc = ".L",
AMD64_COMMON
};
Target T_amd64_apple = {
.name = "amd64_apple",
.apple = 1,
.emitfin = macho_emitfin,
.asloc = "L",
.assym = "_",
AMD64_COMMON
};