Move fold{} from squeeze.singeli to vecfold.singeli
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@ -3,27 +3,12 @@ include './sse'
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include './avx'
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include './avx2'
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include 'util/tup'
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# TODO merge with squeeze
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def fold{F, x:T} = {
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show{'WARNING: using fallback fold'}
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def E = eltype{T}
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r:E = 0
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each{{i} => { r = F{r, extract{x, i}} }, iota{vcount{T}}}
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r
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}
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def fold{F, x:T & width{T}==128 & hasarch{'X86_64'}} = {
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c:= x
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def EW = elwidth{T}
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if (EW<=64) c = F{c, shuf{[4]u32, c, 4b1032}}
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if (EW<=32) c = F{c, shuf{[4]u32, c, 4b2301}}
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if (EW<=16) c = F{c, sel{[16]u8, c, make{[16]i8, iota{16}^2}}}
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if (EW<=8) c = F{c, sel{[16]u8, c, make{[16]i8, iota{16}^1}}}
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extract{c, 0}
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}
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def fold{F, x:T & width{T}==256 & hasarch{'X86_64'}} = fold{F, F{half{x, 0}, half{x, 1}}}
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include './vecfold'
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fn sum_vec{T==[32]i8}(v:T) = fold{+, [16]i16~~fold{+, unpackQ{v, T**0}}}
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def minmax{c, a, b} = tern{c{cast_i{i8,a},cast_i{i8,b}}, a, b}
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def min{a:i16, b:i16} = minmax{<, a, b}
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def max{a:i16, b:i16} = minmax{>, a, b}
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def inc{ptr, ind, v} = store{ptr, ind, v + load{ptr, ind}}
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def inc{ptr, ind} = inc{ptr, ind, 1}
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@ -11,6 +11,7 @@ if (hasarch{'AVX2'}) {
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include './mask'
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include './cbqnDefs'
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include 'util/tup'
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include './vecfold'
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def preserve_negative_zero = 0
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@ -42,30 +43,6 @@ def anyNonChar{M, x:T & isvec{T} & hasarch{'X86_64'}} = {
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def fold{F, x:T} = {
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show{'WARNING: using fallback fold for ', F, T}
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def E = eltype{T}
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r:E = 0
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each{{i} => { r = F{r, extract{x, i}} }, iota{vcount{T}}}
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r
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}
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def fold{F, x:T & w128{T} & hasarch{'X86_64'}} = {
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c:= x
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def EW = elwidth{T}
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if (EW<=64) c = F{c, shuf{[4]u32, c, 4b1032}}
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if (EW<=32) c = F{c, shuf{[4]u32, c, 4b2301}}
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if (hasarch{'SSSE3'} and 0) {
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if (EW<=16) c = F{c, sel{[16]u8, c, make{[16]i8, iota{16}^2}}}
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if (EW==8) c = F{c, sel{[16]u8, c, make{[16]i8, iota{16}^1}}}
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extract{c, 0}
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} else {
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if (EW<=16) c = F{c, shuf16Lo{c, 4b2301}}
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if (EW==8) { v:=extract{[8]i16~~c, 0}; cast_i{u8, F{v, v>>8}} }
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else extract{c, 0}
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}
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}
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def fold{F, x:T & w256{T} & hasarch{'X86_64'}} = fold{F, F{half{x, 0}, half{x, 1}}}
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def makeOptBranch{enable, F} = {
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if (enable) {
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def skip = makelabel{}; goto{skip}
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@ -209,4 +186,4 @@ export{'avx2_squeeze_numB', squeeze{arch_defvw, f64, 0, 1}}
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export{'avx2_squeeze_c16', squeeze{arch_defvw, u16, 1, 0}}
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export{'avx2_squeeze_c32', squeeze{arch_defvw, u32, 1, 0}}
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export{'avx2_squeeze_chrB', squeeze{arch_defvw, u64, 1, 1}}
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export{'avx2_squeeze_chrB', squeeze{arch_defvw, u64, 1, 1}}
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27
src/singeli/src/vecfold.singeli
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27
src/singeli/src/vecfold.singeli
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@ -0,0 +1,27 @@
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# Fold associative/commutative operation across a register
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# Used by squeeze.singeli, count.singeli
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# Has to be included after util/tup because of name conflict
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def fold{F, x:T} = {
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show{'WARNING: using fallback fold for ', F, T}
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def E = eltype{T}
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r:E = 0
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each{{i} => { r = F{r, extract{x, i}} }, iota{vcount{T}}}
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r
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}
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def fold{F, x:T & w128{T} & hasarch{'X86_64'}} = {
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c:= x
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def EW = elwidth{T}
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if (EW<=64) c = F{c, shuf{[4]u32, c, 4b1032}}
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if (EW<=32) c = F{c, shuf{[4]u32, c, 4b2301}}
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if (hasarch{'SSSE3'} and 0) {
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if (EW<=16) c = F{c, sel{[16]u8, c, make{[16]i8, iota{16}^2}}}
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if (EW==8) c = F{c, sel{[16]u8, c, make{[16]i8, iota{16}^1}}}
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extract{c, 0}
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} else {
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if (EW<=16) c = F{c, shuf16Lo{c, 4b2301}}
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if (EW==8) { v:=extract{[8]i16~~c, 0}; cast_i{eltype{T}, F{v, v>>8}} }
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else extract{c, 0}
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}
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}
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def fold{F, x:T & w256{T} & hasarch{'X86_64'}} = fold{F, F{half{x, 0}, half{x, 1}}}
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