From 40ed55bc43a01715d1f90934f7a8e413804e97dd Mon Sep 17 00:00:00 2001 From: Marshall Lochbaum Date: Mon, 11 Sep 2023 21:17:38 -0400 Subject: [PATCH] Use built-in NEON include for basic vector instructions --- build/singeliSubmodule | 2 +- src/singeli/src/base.singeli | 19 ++++++++------- src/singeli/src/neon.singeli | 47 ------------------------------------ 3 files changed, 11 insertions(+), 57 deletions(-) diff --git a/build/singeliSubmodule b/build/singeliSubmodule index eccae1e0..49a6a90d 160000 --- a/build/singeliSubmodule +++ b/build/singeliSubmodule @@ -1 +1 @@ -Subproject commit eccae1e072b0b16d663d7ac243916604de366160 +Subproject commit 49a6a90d83992171a2db749e9f7fd400ec65ef2c diff --git a/src/singeli/src/base.singeli b/src/singeli/src/base.singeli index e80db12c..2fddac94 100644 --- a/src/singeli/src/base.singeli +++ b/src/singeli/src/base.singeli @@ -231,32 +231,33 @@ def has_simd = hasarch{'X86_64'} | hasarch{'AARCH64'} if (hasarch{'X86_64'}) { include 'arch/iintrinsic/basic' - def adds = __adds - def subs = __subs - def sqrt = __sqrt - def broadcast{T, v & isvec{T}} = vec_broadcast{T, promote{eltype{T},v}} - def make{T, ...xs & isvec{T}} = vec_make{T, ...xs} include './sse2' include './sse' include './avx' include './avx2' } else if (hasarch{'AARCH64'}) { + include 'arch/neon_intrin/basic' include './neon' } else { - def {adds,subs,sqrt} + def {__adds,__subs,__sqrt,vec_broadcast,vec_make} } +def broadcast{T, v & isvec{T}} = vec_broadcast{T, promote{eltype{T},v}} +def make{T, ...xs & isvec{T}} = vec_make{T, ...xs} +def iota{T & isvec{T}} = make{T, ...iota{vcount{T}}} +def absu{a:T & isvec{T}} = ty_u{abs{a}} + def floor = __floor def ceil = __ceil def abs = __abs def min = __min def max = __max +def adds = __adds +def subs = __subs +def sqrt = __sqrt def min{a, b & anyNum{a} & anyNum{b}} = tern{ab, a, b} -def absu{a:T & isvec{T}} = ty_u{abs{a}} -def iota{T & isvec{T}} = make{T, ...iota{vcount{T}}} - def load{p,i & kgen{p}} = p{i} def store{p,i,x & kgen{p}} = p{i,x} diff --git a/src/singeli/src/neon.singeli b/src/singeli/src/neon.singeli index cfbc2c07..9fe3e8e6 100644 --- a/src/singeli/src/neon.singeli +++ b/src/singeli/src/neon.singeli @@ -20,36 +20,12 @@ def ntyp{S, ...S2, T & w128{T}} = merge{S, 'q', ...S2, '_', nty{T}} def ntyp{S, ...S2, T & w64{T}} = merge{S, ...S2, '_', nty{T}} def ntyp0{S, T} = merge{S, '_', nty{T}} -def load{a:T, n & nvec{eltype{T}}} = emit{eltype{T}, ntyp{'vld1', eltype{T}}, *eltype{eltype{T}} ~~ (a+n)} -def store{a:*V, n, v:V & nvec{V}} = emit{void, ntyp{'vst1', V}, *eltype{V} ~~ (a+n), v} - -def __or{a:T,b:T & nvecf{T}} = T~~ __or{ty_u{a}, ty_u{b}} -def __and{a:T,b:T & nvecf{T}} = T~~__and{ty_u{a}, ty_u{b}} -def __xor{a:T,b:T & nvecf{T}} = T~~__xor{ty_u{a}, ty_u{b}} -def __add{a:T,b:T & nvec {T}} = emit{T, ntyp{'vadd', T}, a, b} -def __sub{a:T,b:T & nvec {T}} = emit{T, ntyp{'vsub', T}, a, b} -def __mul{a:T,b:T & nvec {T}} = emit{T, ntyp{'vmul', T}, a, b} -def __div{a:T,b:T & nvecf{T}} = emit{T, ntyp{'vdiv', T}, a, b} -def __and{a:T,b:T & nveci{T}} = emit{T, ntyp{'vand', T}, a, b} -def __or{a:T,b:T & nveci{T}} = emit{T, ntyp{'vorr', T}, a, b} -def __xor{a:T,b:T & nveci{T}} = emit{T, ntyp{'veor', T}, a, b} -def andnot{a:T,b:T & nveci{T}} = emit{T, ntyp{'vbic', T}, a, b} -def ornot{a:T,b:T & nveci{T}} = emit{T, ntyp{'vorn', T}, a, b} -def andnz{a:T,b:T & nveci{T}} = emit{T, ntyp{'vtst', T}, a, b} -def __min{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmin', T}, a, b} -def __max{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmax', T}, a, b} -def __shl{a:T,b:S & nveci{T} & nveci{S,elwidth{T}}} = emit{T, ntyp{'vshl', T}, a, ty_s{b}} -def adds{a:T,b:T & nveci{T}} = emit{T, ntyp{'vqadd', T}, a, b} -def subs{a:T,b:T & nveci{T}} = emit{T, ntyp{'vqsub', T}, a, b} -def addp{a:T,b:T & nvec{T}} = emit{T, ntyp{'vpadd', T}, a, b} def addwLo{a:T,b:T & w64i{T}} = emit{el_d{T}, ntyp{'vaddl', T}, a, b} def subwLo{a:T,b:T & w64i{T}} = emit{el_d{T}, ntyp{'vsubl', T}, a, b} def mulwLo{a:T,b:T & w64i{T}} = emit{el_d{T}, ntyp{'vmull', T}, a, b} def mulwHi{a:T,b:T & w128i{T}} = emit{el_m{T}, ntyp0{'vmull_high', T}, a, b} def mulw {a:T,b:T & w128{T}} = tup{mulwLo{half{a,0}, half{b,0}}, mulwHi{a,b}} -def __shl{a:T, s & nveci{T} & knum{s} & s>0 & s0 & s8} = { def H=el_h{T}; emit{H, ntyp0{'vshrn_n', T}, a, s} } # a>>s, narrowed def shrm{a:T, s, d:T & nvecu{T}} = emit{T, ntyp{'vsri', '_n', T}, d, a, s} # (a>>s) | (d & (mask of new zeroes)) def shlm{a:T, s, d:T & nvecu{T}} = emit{T, ntyp{'vsli', '_n', T}, d, a, s} # (a<=vcount{T}} = { truncBits{vcount{T}, fold_add{x & make{T, 1<