fix WARN_SLOW build

This commit is contained in:
dzaima 2022-09-12 18:16:37 +03:00
parent fa4c5424d3
commit 47c4a53da4
2 changed files with 12 additions and 11 deletions

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@ -26,8 +26,8 @@ B floor_c2(B, B, B);
#include "../singeli/c/arithdDispatch.c" #include "../singeli/c/arithdDispatch.c"
#endif #endif
#define ARITH_SLOW SLOWIF((!isArr(w) || TI(w,elType)!=el_B) && (!isArr(x) || TI(x,elType)!=el_B)) SLOW2("arithd " #N, w, x) #define ARITH_SLOW(N) SLOWIF((!isArr(w) || TI(w,elType)!=el_B) && (!isArr(x) || TI(x,elType)!=el_B)) SLOW2("arithd " #N, w, x)
#define P2(N) { if(isArr(w)|isArr(x)) { ARITH_SLOW; \ #define P2(N) { if(isArr(w)|isArr(x)) { ARITH_SLOW(N); \
return arith_recd(N##_c2, w, x); \ return arith_recd(N##_c2, w, x); \
}} }}
#if !TYPED_ARITH #if !TYPED_ARITH
@ -181,7 +181,7 @@ B floor_c2(B, B, B);
if(we==el_i32 & xe==el_i16) { PI32(w) PI16(x) DOI32(EXPR,w,wp[i],xp[i],bad) } \ if(we==el_i32 & xe==el_i16) { PI32(w) PI16(x) DOI32(EXPR,w,wp[i],xp[i],bad) } \
if(we==el_i16 & xe==el_i8 ) { PI16(w) PI8 (x) DOI16(EXPR,w,wp[i],xp[i],bad) } \ if(we==el_i16 & xe==el_i8 ) { PI16(w) PI8 (x) DOI16(EXPR,w,wp[i],xp[i],bad) } \
if(we==el_i8 & xe==el_i16) { PI8 (w) PI16(x) DOI16(EXPR,w,wp[i],xp[i],bad) } \ if(we==el_i8 & xe==el_i16) { PI8 (w) PI16(x) DOI16(EXPR,w,wp[i],xp[i],bad) } \
bad: ARITH_SLOW; return arith_recd(NAME##_c2, w, x); \ bad: ARITH_SLOW(CHR); return arith_recd(NAME##_c2, w, x); \
dec_ret: decG(w); decG(x); return r; \ dec_ret: decG(w); decG(x); return r; \
} }
AR_I_AA("×", mul, wv*xv, 2, {}) AR_I_AA("×", mul, wv*xv, 2, {})
@ -206,14 +206,14 @@ B floor_c2(B, B, B);
#define AR_I_AS(CHR, NAME, EXPR, DO_AS, EXTRA) NOINLINE B NAME##_AS(B t, B w, B x) { \ #define AR_I_AS(CHR, NAME, EXPR, DO_AS, EXTRA) NOINLINE B NAME##_AS(B t, B w, B x) { \
B r; u8 we=TI(w,elType); EXTRA \ B r; u8 we=TI(w,elType); EXTRA \
if (isF64(x)) { usz ia=IA(w); DO_AS(NAME,EXPR) } \ if (isF64(x)) { usz ia=IA(w); DO_AS(NAME,EXPR) } \
ARITH_SLOW; return arith_recd(NAME##_c2, w, x); \ ARITH_SLOW(CHR); return arith_recd(NAME##_c2, w, x); \
dec_ret: decG(w); return r; \ dec_ret: decG(w); return r; \
} }
#define AR_I_SA(CHR, NAME, EXPR, DO_SA, EXTRA) NOINLINE B NAME##_SA(B t, B w, B x) { \ #define AR_I_SA(CHR, NAME, EXPR, DO_SA, EXTRA) NOINLINE B NAME##_SA(B t, B w, B x) { \
B r; u8 xe=TI(x,elType); EXTRA \ B r; u8 xe=TI(x,elType); EXTRA \
if (isF64(w)) { usz ia=IA(x); DO_SA(NAME,EXPR) } \ if (isF64(w)) { usz ia=IA(x); DO_SA(NAME,EXPR) } \
ARITH_SLOW; return arith_recd(NAME##_c2, w, x); \ ARITH_SLOW(CHR); return arith_recd(NAME##_c2, w, x); \
dec_ret: decG(x); return r; \ dec_ret: decG(x); return r; \
} }

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@ -27,6 +27,7 @@ make f='-DLOG_GC' c && ./BQN -p 2+2 || exit
make f='-DWRITE_ASM' c && ./BQN -p 2+2 || exit make f='-DWRITE_ASM' c && ./BQN -p 2+2 || exit
make f='-DUSE_PERF' c && ./BQN -p 2+2 || exit make f='-DUSE_PERF' c && ./BQN -p 2+2 || exit
make f='-DUSZ_64' c && ./BQN -p 2+2 || exit make f='-DUSZ_64' c && ./BQN -p 2+2 || exit
make f='-DWARN_SLOW' c && ./BQN -p 2+2 || exit
make f='-DREPL_INTERRUPT=0' c && ./BQN -p 2+2 || exit make f='-DREPL_INTERRUPT=0' c && ./BQN -p 2+2 || exit
make f='-DREPL_INTERRUPT=1' c && ./BQN -p 2+2 || exit make f='-DREPL_INTERRUPT=1' c && ./BQN -p 2+2 || exit
make FFI=0 c && ./BQN -p 2+2 || exit make FFI=0 c && ./BQN -p 2+2 || exit