fix WARN_SLOW build
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@ -26,8 +26,8 @@ B floor_c2(B, B, B);
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#include "../singeli/c/arithdDispatch.c"
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#include "../singeli/c/arithdDispatch.c"
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#endif
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#endif
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#define ARITH_SLOW SLOWIF((!isArr(w) || TI(w,elType)!=el_B) && (!isArr(x) || TI(x,elType)!=el_B)) SLOW2("arithd " #N, w, x)
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#define ARITH_SLOW(N) SLOWIF((!isArr(w) || TI(w,elType)!=el_B) && (!isArr(x) || TI(x,elType)!=el_B)) SLOW2("arithd " #N, w, x)
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#define P2(N) { if(isArr(w)|isArr(x)) { ARITH_SLOW; \
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#define P2(N) { if(isArr(w)|isArr(x)) { ARITH_SLOW(N); \
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return arith_recd(N##_c2, w, x); \
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return arith_recd(N##_c2, w, x); \
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}}
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}}
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#if !TYPED_ARITH
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#if !TYPED_ARITH
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@ -181,7 +181,7 @@ B floor_c2(B, B, B);
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if(we==el_i32 & xe==el_i16) { PI32(w) PI16(x) DOI32(EXPR,w,wp[i],xp[i],bad) } \
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if(we==el_i32 & xe==el_i16) { PI32(w) PI16(x) DOI32(EXPR,w,wp[i],xp[i],bad) } \
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if(we==el_i16 & xe==el_i8 ) { PI16(w) PI8 (x) DOI16(EXPR,w,wp[i],xp[i],bad) } \
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if(we==el_i16 & xe==el_i8 ) { PI16(w) PI8 (x) DOI16(EXPR,w,wp[i],xp[i],bad) } \
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if(we==el_i8 & xe==el_i16) { PI8 (w) PI16(x) DOI16(EXPR,w,wp[i],xp[i],bad) } \
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if(we==el_i8 & xe==el_i16) { PI8 (w) PI16(x) DOI16(EXPR,w,wp[i],xp[i],bad) } \
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bad: ARITH_SLOW; return arith_recd(NAME##_c2, w, x); \
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bad: ARITH_SLOW(CHR); return arith_recd(NAME##_c2, w, x); \
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dec_ret: decG(w); decG(x); return r; \
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dec_ret: decG(w); decG(x); return r; \
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}
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}
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AR_I_AA("×", mul, wv*xv, 2, {})
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AR_I_AA("×", mul, wv*xv, 2, {})
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@ -206,14 +206,14 @@ B floor_c2(B, B, B);
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#define AR_I_AS(CHR, NAME, EXPR, DO_AS, EXTRA) NOINLINE B NAME##_AS(B t, B w, B x) { \
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#define AR_I_AS(CHR, NAME, EXPR, DO_AS, EXTRA) NOINLINE B NAME##_AS(B t, B w, B x) { \
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B r; u8 we=TI(w,elType); EXTRA \
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B r; u8 we=TI(w,elType); EXTRA \
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if (isF64(x)) { usz ia=IA(w); DO_AS(NAME,EXPR) } \
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if (isF64(x)) { usz ia=IA(w); DO_AS(NAME,EXPR) } \
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ARITH_SLOW; return arith_recd(NAME##_c2, w, x); \
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ARITH_SLOW(CHR); return arith_recd(NAME##_c2, w, x); \
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dec_ret: decG(w); return r; \
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dec_ret: decG(w); return r; \
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}
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}
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#define AR_I_SA(CHR, NAME, EXPR, DO_SA, EXTRA) NOINLINE B NAME##_SA(B t, B w, B x) { \
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#define AR_I_SA(CHR, NAME, EXPR, DO_SA, EXTRA) NOINLINE B NAME##_SA(B t, B w, B x) { \
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B r; u8 xe=TI(x,elType); EXTRA \
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B r; u8 xe=TI(x,elType); EXTRA \
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if (isF64(w)) { usz ia=IA(x); DO_SA(NAME,EXPR) } \
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if (isF64(w)) { usz ia=IA(x); DO_SA(NAME,EXPR) } \
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ARITH_SLOW; return arith_recd(NAME##_c2, w, x); \
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ARITH_SLOW(CHR); return arith_recd(NAME##_c2, w, x); \
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dec_ret: decG(x); return r; \
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dec_ret: decG(x); return r; \
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}
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}
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@ -27,6 +27,7 @@ make f='-DLOG_GC' c && ./BQN -p 2+2 || exit
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make f='-DWRITE_ASM' c && ./BQN -p 2+2 || exit
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make f='-DWRITE_ASM' c && ./BQN -p 2+2 || exit
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make f='-DUSE_PERF' c && ./BQN -p 2+2 || exit
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make f='-DUSE_PERF' c && ./BQN -p 2+2 || exit
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make f='-DUSZ_64' c && ./BQN -p 2+2 || exit
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make f='-DUSZ_64' c && ./BQN -p 2+2 || exit
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make f='-DWARN_SLOW' c && ./BQN -p 2+2 || exit
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make f='-DREPL_INTERRUPT=0' c && ./BQN -p 2+2 || exit
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make f='-DREPL_INTERRUPT=0' c && ./BQN -p 2+2 || exit
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make f='-DREPL_INTERRUPT=1' c && ./BQN -p 2+2 || exit
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make f='-DREPL_INTERRUPT=1' c && ./BQN -p 2+2 || exit
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make FFI=0 c && ./BQN -p 2+2 || exit
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make FFI=0 c && ./BQN -p 2+2 || exit
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