Move x86 vector and NEON includes into base.singeli
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@ -176,7 +176,7 @@ def maxvalue{T & issigned{T}} = (1<<(width{T}-1))-1
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# base cases
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def {
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andAllZero,andnz,b_getBatch,clmul,cvt,fold_addw,half,
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absu,andAllZero,andnz,b_getBatch,clmul,cvt,extract,fold_addw,half,
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homAll,homAny,homBlend,homMask,homMaskStore,homMaskStoreF,loadBatchBit,
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loadLow,make,mulw,mulHi,narrow,narrowPair,packHi,packLo,packQ,pair,pdep,
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pext,popcRand,sel,shl,shr,shuf,shuf16Hi,shuf16Lo,shufHalves,storeLow,
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@ -196,11 +196,6 @@ def packQ{{a, b}} = packQ{a, b}
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def pair{{a, b}} = pair{a, b}
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def cvt{T, x:X & T==eltype{X}} = x
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def min{...x} = __min{...x}
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def max{...x} = __max{...x}
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def __min{a, b & anyNum{a} & anyNum{b}} = tern{a<b, a, b}
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def __max{a, b & anyNum{a} & anyNum{b}} = tern{a>b, a, b}
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def homMask{...vs & tuplen{vs}>1} = {
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def n = tuplen{vs}
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def T = oneType{vs}
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@ -234,6 +229,34 @@ def broadcast{n, v & knum{n}} = each{{_}=>v, range{n}}
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def arch_defvw = tern{hasarch{'AVX2'}, 256, 128}
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def has_simd = hasarch{'X86_64'} | hasarch{'AARCH64'}
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if (hasarch{'X86_64'}) {
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include 'arch/iintrinsic/basic'
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def adds = __adds
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def subs = __subs
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def sqrt = __sqrt
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def broadcast{T, v & isvec{T}} = vec_broadcast{T, promote{eltype{T},v}}
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def make{T, ...xs & isvec{T}} = vec_make{T, ...xs}
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include './sse2'
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include './sse'
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include './avx'
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include './avx2'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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} else {
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def {adds,subs,sqrt}
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}
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def floor = __floor
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def ceil = __ceil
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def abs = __abs
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def min = __min
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def max = __max
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def min{a, b & anyNum{a} & anyNum{b}} = tern{a<b, a, b}
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def max{a, b & anyNum{a} & anyNum{b}} = tern{a>b, a, b}
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def absu{a:T & isvec{T}} = ty_u{abs{a}}
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def iota{T & isvec{T}} = make{T, ...iota{vcount{T}}}
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def load{p,i & kgen{p}} = p{i}
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def store{p,i,x & kgen{p}} = p{i,x}
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@ -1,8 +1,5 @@
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include './base'
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include './cbqnDefs'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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}
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include './mask'
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include 'util/tup'
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@ -1,10 +1,5 @@
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include './base'
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include './cbqnDefs'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './f64'
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include './bitops'
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include './mask'
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@ -1,10 +1,5 @@
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include './base'
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include './cbqnDefs'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './f64'
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include './bitops'
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@ -1,9 +1,4 @@
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include './base'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './mask'
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include 'util/tup'
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def incl{a,b} = slice{iota{b+1},a}
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@ -1,9 +1,4 @@
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include './base'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './mask'
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include './cbqnDefs'
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include './bitops'
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@ -1,5 +1,4 @@
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include './base'
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include './x86_vec'
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include 'util/tup'
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include './vecfold'
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@ -1,10 +1,5 @@
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include './base'
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include './cbqnDefs'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './f64'
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include './bitops'
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include './mask'
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@ -1,10 +1,5 @@
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include './base'
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include './cbqnDefs'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './f64'
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include './mask'
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include './bitops'
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@ -1,9 +1,4 @@
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include './base'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './mask'
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def opsh64{op}{v:[4]f64, perm} = op{v, shuf{[4]u64, v, perm}}
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@ -1,10 +1,5 @@
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include './base'
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include './cbqnDefs'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './f64'
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include './bitops'
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include './mask'
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@ -36,8 +36,8 @@ def __xor{a:T,b:T & nveci{T}} = emit{T, ntyp{'veor', T}, a, b}
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def andnot{a:T,b:T & nveci{T}} = emit{T, ntyp{'vbic', T}, a, b}
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def ornot{a:T,b:T & nveci{T}} = emit{T, ntyp{'vorn', T}, a, b}
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def andnz{a:T,b:T & nveci{T}} = emit{T, ntyp{'vtst', T}, a, b}
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def min{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmin', T}, a, b}
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def max{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmax', T}, a, b}
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def __min{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmin', T}, a, b}
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def __max{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmax', T}, a, b}
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def __shl{a:T,b:S & nveci{T} & nveci{S,elwidth{T}}} = emit{T, ntyp{'vshl', T}, a, ty_s{b}}
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def adds{a:T,b:T & nveci{T}} = emit{T, ntyp{'vqadd', T}, a, b}
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def subs{a:T,b:T & nveci{T}} = emit{T, ntyp{'vqsub', T}, a, b}
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@ -57,13 +57,12 @@ def shlm{a:T, s, d:T & nvecu{T}} = emit{T, ntyp{'vsli', '_n', T}, d, a, s} # (a
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def bitBlend{f:T, t:T, m:M & nvec{T} & nvecu{M,elwidth{T}} & width{T}==width{M}} = emit{T, ntyp{'vbsl', T}, m, t, f}
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def homBlend{f:T, t:T, m:M & nvec{M}} = bitBlend{f, t, m}
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def __neg{a:T & (nvecs{T}|nvecf{T})} = emit{T, ntyp{'vneg', T}, a}
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def __not{a:T & nvecu{T}} = T~~emit{re_el{u8,T}, ntyp{'vmvn', re_el{u8,T}}, a}
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def sqrt{a:T & nvecf{T}} = emit{T, ntyp{'vsqrt', T}, a}
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def floor{a:T & nvecf{T}} = emit{T, ntyp{'vrndm', T}, a}
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def ceil{a:T & nvecf{T}} = emit{T, ntyp{'vrndp', T}, a}
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def abs{a:T & (nvecs{T}|nvecf{T})} = emit{T, ntyp{'vabs', T}, a}
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def absu{a:T & nveci{T}} = ty_u{abs{a}}
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def __neg{a:T & (nvecs{T}|nvecf{T})} = emit{T, ntyp{'vneg', T}, a}
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def __not{a:T & nvecu{T}} = T~~emit{re_el{u8,T}, ntyp{'vmvn', re_el{u8,T}}, a}
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def sqrt{a:T & nvecf{T}} = emit{T, ntyp{'vsqrt', T}, a}
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def __floor{a:T & nvecf{T}} = emit{T, ntyp{'vrndm', T}, a}
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def __ceil{a:T & nvecf{T}} = emit{T, ntyp{'vrndp', T}, a}
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def __abs{a:T & (nvecs{T}|nvecf{T})} = emit{T, ntyp{'vabs', T}, a}
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def addpw { x:T & nveci{T} & elwidth{T}<=32 } = emit{el_m{T}, ntyp{'vpaddl', T}, x} # add pairwise widening
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def addpwa{a:D, x:T & nveci{T} & elwidth{T}<=32 & D==el_m{T}} = emit{D, ntyp{'vpadal', T}, a, x} # add pairwise widening + accumulate
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def mla{a:T, x:T, y:T & nvec{T}} = emit{T, ntyp{'vmla', T}, a, x, y} # a + x*y
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@ -168,7 +167,6 @@ def make{T, ...xs & nvec{T} & tuplen{xs}==vcount{T}} = {
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load{*T ~~ *TE ~~ each{promote{eltype{T},.}, xs}, 0}
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}
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def make{T, x & nvec{T} & istup{x}} = make{T, ...x}
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def iota{T & nvec{T}} = make{T, ...iota{vcount{T}}}
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def homMask{x:T & nvecu{T} & elwidth{T}>=vcount{T}} = {
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@ -1,7 +1,4 @@
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include './base'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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}
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include './clmul'
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include './mask'
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include './f64'
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@ -1,9 +1,4 @@
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include './base'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './mask'
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include './vecfold'
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@ -1,6 +1,5 @@
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include './base'
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include './cbqnDefs'
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include './x86_vec'
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include './mask'
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include './bitops'
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include 'util/tup'
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@ -1,10 +1,7 @@
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include './base'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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if (hasarch{'PCLMUL'}) include './clmul'
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if (hasarch{'BMI2'}) include './bmi2'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './mask'
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include 'util/tup'
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@ -1,9 +1,4 @@
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include './base'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './mask'
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include './cbqnDefs'
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include 'util/tup'
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@ -1,10 +1,5 @@
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include './base'
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include './cbqnDefs'
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if (hasarch{'X86_64'}) {
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include './x86_vec'
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} else if (hasarch{'AARCH64'}) {
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include './neon'
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}
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include './f64'
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include './mask'
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include './bitops'
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@ -1,15 +0,0 @@
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include 'arch/iintrinsic/basic'
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def adds = __adds
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def subs = __subs
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def sqrt = __sqrt
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def floor = __floor
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def ceil = __ceil
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def abs = __abs
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def broadcast{T, v & isvec{T}} = vec_broadcast{T, promote{eltype{T},v}}
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def make{T, ...xs & isvec{T}} = vec_make{T, ...xs}
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def iota{T & isvec{T}} = make{T, ...iota{vcount{T}}}
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def absu{a:T & isvec{T}} = ty_u{abs{a}}
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include './sse2'
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include './sse'
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include './avx'
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include './avx2'
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