prep for NEON squeeze

This commit is contained in:
dzaima 2023-01-24 22:21:38 +02:00
parent f91d3dfaf5
commit 88410c02e5
6 changed files with 28 additions and 10 deletions

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@ -77,7 +77,7 @@ Additionally, CBQN is known to compile as-is on macOS, but Windows requires [Win
## License ## License
Most files here are copyright (c) 2021 dzaima & others, [GNU GPLv3 only](licenses/LICENSE-GPLv3). Most files here are copyright (c) 2021-2023 dzaima & others, [GNU GPLv3 only](licenses/LICENSE-GPLv3).
Exceptions are: Exceptions are:
- timsort implementation - `src/builtins/sortTemplate.h`: [MIT](licenses/LICENSE-MIT-sort); [original repo](https://github.com/swenson/sort/tree/f79f2a525d03f102034b5a197c395f046eb82708) - timsort implementation - `src/builtins/sortTemplate.h`: [MIT](licenses/LICENSE-MIT-sort); [original repo](https://github.com/swenson/sort/tree/f79f2a525d03f102034b5a197c395f046eb82708)
- Ryu - `src/utils/ryu.c` & files in `src/utils/ryu/`: [Apache 2.0](licenses/LICENSE-Apache2) or [Boost 1.0](licenses/LICENSE-Boost); [original repo](https://github.com/ulfjack/ryu/tree/75d5a85440ed356ad7b23e9e6002d71f62a6255c) - Ryu - `src/utils/ryu.c` & files in `src/utils/ryu/`: [Apache 2.0](licenses/LICENSE-Apache2) or [Boost 1.0](licenses/LICENSE-Boost); [original repo](https://github.com/ulfjack/ryu/tree/75d5a85440ed356ad7b23e9e6002d71f62a6255c)

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@ -31,6 +31,10 @@ NOINLINE B num_squeezeF(B x, usz ia) {
B num_squeeze(B x) { B num_squeeze(B x) {
usz ia = IA(x); usz ia = IA(x);
u8 xe = TI(x,elType); u8 xe = TI(x,elType);
if (ia==0) {
if (xe==el_bit) return x;
goto r_bit;
}
#if !SINGELI_X86_64 #if !SINGELI_X86_64
usz i = 0; usz i = 0;

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@ -120,6 +120,13 @@ def mul12{...x} = assert{'mul12 not supported', show{...x}}
def unpackQ{...x} = assert{'unpackQ not supported', show{...x}} def unpackQ{...x} = assert{'unpackQ not supported', show{...x}}
def packQ{...x} = assert{'packQ not supported', show{...x}} def packQ{...x} = assert{'packQ not supported', show{...x}}
def __mulhi{...x} = assert{'__mulhi not supported', show{...x}} def __mulhi{...x} = assert{'__mulhi not supported', show{...x}}
def fold_max {...x} = assert{'fold_max not supported', show{...x}}
def fold_min {...x} = assert{'fold_min not supported', show{...x}}
def fold_add {...x} = assert{'fold_add not supported', show{...x}}
def fold_addw{...x} = assert{'fold_addw not supported', show{...x}}
def cvt{...x} = assert{'cvt not supported', show{...x}}
def cvt{T, x:X & T==eltype{X}} = x
def shuf{...x} = assert{'shuf not supported', show{...x}}
def min{a, b & knum{a} & knum{b}} = tern{a<b, a, b} def min{a, b & knum{a} & knum{b}} = tern{a<b, a, b}
def max{a, b & knum{a} & knum{b}} = tern{a>b, a, b} def max{a, b & knum{a} & knum{b}} = tern{a>b, a, b}

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@ -12,6 +12,7 @@ local def maskOfImpl{T, n, w} = load{*ty_u{T} ~~ (*u8~~mask256 + 32 - n*(elwidth
# get mask of first n items; 0 ≤ n ≤ vcount{T} # get mask of first n items; 0 ≤ n ≤ vcount{T}
def maskOf{T,n & width{T}==256} = maskOfImpl{T, n, 256} def maskOf{T,n & width{T}==256} = maskOfImpl{T, n, 256}
def maskOf{T,n & width{T}==128} = maskOfImpl{T, n, 128} def maskOf{T,n & width{T}==128} = maskOfImpl{T, n, 128}
def maskOf{T,n & width{T}== 64} = maskOfImpl{T, n, 64}
def anyne{x:T, y:T, M & M{0}==0 & isvec{T}} = ~homAll{x==y} def anyne{x:T, y:T, M & M{0}==0 & isvec{T}} = ~homAll{x==y}
def anyne{x:T, y:T, M & M{0}==1 & isvec{T}} = homAny{M{x!=y}} def anyne{x:T, y:T, M & M{0}==1 & isvec{T}} = homAny{M{x!=y}}

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@ -47,8 +47,8 @@ def min{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmin', T}, a, b}
def max{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmax', T}, a, b} def max{a:T,b:T & nvec{T}} = emit{T, ntyp{'vmax', T}, a, b}
def __shl{a:T,b:S & nveci{T} & nveci{S} & elwidth{T}==elwidth{S}} = emit{T, ntyp{'vshl', T}, a, ty_s{b}} def __shl{a:T,b:S & nveci{T} & nveci{S} & elwidth{T}==elwidth{S}} = emit{T, ntyp{'vshl', T}, a, ty_s{b}}
def __shl{a:T,b & nveci{T} & knum{b}} = emit{T, ntyp{'vshl', '_n', T}, a, b}; def __shl{a:T,b==0 & nveci{T}} = a def __shl{a:T,b & nveci{T} & knum{b} & b>0 & b<elwidth{T}} = emit{T, ntyp{'vshl', '_n', T}, a, b}; def __shl{a:T,b==0 & nveci{T}} = a
def __shr{a:T,b & nveci{T} & knum{b}} = emit{T, ntyp{'vshr', '_n', T}, a, b}; def __shr{a:T,b==0 & nveci{T}} = a def __shr{a:T,b & nveci{T} & knum{b} & b>0 & b<elwidth{T}} = emit{T, ntyp{'vshr', '_n', T}, a, b}; def __shr{a:T,b==0 & nveci{T}} = a
def bitBlend{f:T, t:T, m:M & nvec{T} & nvecu{M} & width{T}==width{M} & elwidth{T}==elwidth{M}} = emit{T, ntyp{'vbsl', T}, m, t, f} def bitBlend{f:T, t:T, m:M & nvec{T} & nvecu{M} & width{T}==width{M} & elwidth{T}==elwidth{M}} = emit{T, ntyp{'vbsl', T}, m, t, f}
def homBlend{f:T, t:T, m:M & nvec{M}} = bitBlend{f, t, m} def homBlend{f:T, t:T, m:M & nvec{M}} = bitBlend{f, t, m}
@ -73,8 +73,8 @@ def __ne{a:T,b:T & nvec{T}} = ~(a==b)
def fold_add {a:T & nvec{T}} = emit{eltype{T}, ntyp{'vaddv', T}, a} def fold_add {a:T & nvec{T}} = emit{eltype{T}, ntyp{'vaddv', T}, a}
def fold_addw{a:T & nvec{T}} = emit{ty_dbl{eltype{T}}, ntyp{'vaddlv', T}, a} def fold_addw{a:T & nvec{T}} = emit{ty_dbl{eltype{T}}, ntyp{'vaddlv', T}, a}
def fold_min {a:T & nvec{T}} = emit{eltype{T}, ntyp{'vminv', T}, a} def fold_min {a:T & nvec{T} & elwidth{T}<=32} = emit{eltype{T}, ntyp{'vminv', T}, a}
def fold_max {a:T & nvec{T}} = emit{eltype{T}, ntyp{'vmaxv', T}, a} def fold_max {a:T & nvec{T} & elwidth{T}<=32} = emit{eltype{T}, ntyp{'vmaxv', T}, a}
# TODO don't rely on regular stores being unaligned # TODO don't rely on regular stores being unaligned
local def storeu{ptr:P, e:T} = store{ptr, 0, e} local def storeu{ptr:P, e:T} = store{ptr, 0, e}
@ -112,11 +112,13 @@ def sel{L, x:T, i:I & lvec{L,16,8} & n128{T} & nvec{I, 8}} = to_el{eltype{T}, em
local def eqqi{A, B} = isint{A} & (quality{A}==quality{B}) # equal quality integers local def eqqi{A, B} = isint{A} & (quality{A}==quality{B}) # equal quality integers
def cvt{T, x:X & width{T}==width{X} & nvecf{T,64} & nveci{X}} = emit{T, ntyp{'vcvt', '_f64', X}, x} def cvt{T==f64, x:X & nveci{X,64}} = emit{[vcount{X}]T, ntyp{'vcvt', '_f64', X}, x}
def cvt{T==i64, x:X & nvecf{X,64}} = emit{[vcount{X}]T, ntyp{'vcvt', '_s64', X}, x}
def cvt{T==u64, x:X & nvecf{X,64}} = emit{[vcount{X}]T, ntyp{'vcvt', '_u64', X}, x}
def widen{T, x:X & n64{X} & eqqi{eltype{T},eltype{X}} & elwidth{T}==elwidth{X}*2} = emit{T, ntyp{'vmovl', X}, x} def widen{T, x:X & n64{X} & eqqi{eltype{T},eltype{X}} & elwidth{T}==elwidth{X}*2} = emit{T, ntyp{'vmovl', X}, x}
def widen{T, x:X & n64{X} & eqqi{eltype{T},eltype{X}} & elwidth{T}> elwidth{X}*2} = widen{T, widen{ty_half{T}, x}} def widen{T, x:X & n64{X} & eqqi{eltype{T},eltype{X}} & elwidth{T}> elwidth{X}*2} = widen{T, widen{ty_half{T}, x}}
def widen{T, x:X & n64{X} & isfloat{eltype{T}}!=isfloat{eltype{X}} & elwidth{T}>elwidth{X}} = cvt{T, widen{[vcount{T}](to_w{eltype{X},elwidth{T}}), x}} def widen{T, x:X & n64{X} & isfloat{eltype{T}}!=isfloat{eltype{X}} & elwidth{T}>elwidth{X}} = cvt{eltype{T}, widen{[vcount{T}](to_w{eltype{X},elwidth{T}}), x}}
def widen{T, x:X & n128{X} & vcount{X}>vcount{T}} = widen{T, half{x,0}} def widen{T, x:X & n128{X} & vcount{X}>vcount{T}} = widen{T, half{x,0}}
def narrow{T, x:X & n128{X} & eqqi{T,eltype{X}} & width{T}*2< elwidth{X}} = narrow{T, undefPromote{ty_half{X}, narrow{ty_half{eltype{X}}, x}}} def narrow{T, x:X & n128{X} & eqqi{T,eltype{X}} & width{T}*2< elwidth{X}} = narrow{T, undefPromote{ty_half{X}, narrow{ty_half{eltype{X}}, x}}}

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@ -1,7 +1,11 @@
include './base' include './base'
include './sse3' if (hasarch{'X86_64'}) {
include './avx' include './sse3'
include './avx2' include './avx'
include './avx2'
} else if (hasarch{'AARCH64'}) {
include './neon'
}
include './mask' include './mask'
include './cbqnDefs' include './cbqnDefs'
include 'util/tup' include 'util/tup'