135 lines
4.3 KiB
C
135 lines
4.3 KiB
C
#include <assert.h>
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#include "src/cyw43.h"
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#include "src/cyw43_internal.h"
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#define BACKPLANE_BASE_ADDRESS (0x00000000)
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#define BACKPLANE_RAM_SIZE (512 * 1024)
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#define CHIPCOMMON_BASE_ADDRESS (0x18000000)
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// BUS_FUNCTION addresses.
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#define SDIOD_CCCR_IOEN (0x02)
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#define SDIOD_CCCR_IORDY (0x03)
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#define SDIOD_CCCR_BLKSIZE_0 (0x10)
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#define SDIOD_CCCR_SPEED_CONTROL (0x13)
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// BACKPLANE_FUNCTION addresses.
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#define SDIO_BACKPLANE_ADDRESS_LOW (0x1000a)
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#define SDIO_BACKPLANE_ADDRESS_MID (0x1000b)
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#define SDIO_BACKPLANE_ADDRESS_HIGH (0x1000c)
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#define SDIO_CHIP_CLOCK_CSR (0x1000e)
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#define SDIO_FUNC_ENABLE_1 (0x02)
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#define SDIO_FUNC_READY_1 (0x02)
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#define SBSDIO_ALP_AVAIL (0x40)
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#define SBSDIO_HT_AVAIL (0x80)
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static uint8_t sdiod_cccr_blksize_0;
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static uint32_t sdio_backplane_cur_addr = 0;
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static uint8_t backplane_ram[BACKPLANE_RAM_SIZE];
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void cyw43_sdio_init(void) {
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printf("cyw43_sdio_init()\n");
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}
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void cyw43_sdio_reinit(void) {
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printf("cyw43_sdio_reinit()\n");
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}
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void cyw43_sdio_deinit(void) {
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printf("cyw43_sdio_deinit()\n");
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}
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void cyw43_sdio_set_irq(bool enable) {
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printf("cyw43_sdio_set_irq(%u)\n", enable);
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}
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void cyw43_sdio_enable_high_speed_4bit(void) {
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printf("cyw43_sdio_enable_high_speed_4bit()\n");
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}
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int cyw43_sdio_transfer(uint32_t cmd, uint32_t arg, uint32_t *resp) {
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printf("cyw43_sdio_transfer(cmd=%u, arg=%08x)\n", cmd, arg);
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if (resp != NULL) {
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*resp = 0;
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}
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if (cmd == 52) {
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uint32_t write = (arg >> 31) & 1;
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uint32_t fn = (arg >> 28) & 0x7;
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uint32_t addr = (arg >> 9) & 0x1ffff;
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uint32_t val = arg & 0xff;
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if (fn == BUS_FUNCTION) {
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if (addr == SDIOD_CCCR_IOEN) {
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if (write == 0) {
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*resp = SDIO_FUNC_ENABLE_1;
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}
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} else if (addr == SDIOD_CCCR_IORDY) {
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if (write == 0) {
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*resp = SDIO_FUNC_READY_1;
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}
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} else if (addr == SDIOD_CCCR_BLKSIZE_0) {
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if (write == 0) {
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*resp = sdiod_cccr_blksize_0;
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} else {
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sdiod_cccr_blksize_0 = val;
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}
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} else if (addr == SDIOD_CCCR_SPEED_CONTROL) {
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if (write == 0) {
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*resp = 1; // bus supports high-speed mode
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}
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}
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} else if (fn == BACKPLANE_FUNCTION) {
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if (addr == SDIO_BACKPLANE_ADDRESS_LOW) {
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sdio_backplane_cur_addr = (sdio_backplane_cur_addr & 0xffff00ff) | (val << 8);
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} else if (addr == SDIO_BACKPLANE_ADDRESS_MID) {
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sdio_backplane_cur_addr = (sdio_backplane_cur_addr & 0xff00ffff) | (val << 16);
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} else if (addr == SDIO_BACKPLANE_ADDRESS_HIGH) {
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sdio_backplane_cur_addr = (sdio_backplane_cur_addr & 0x00ffffff) | (val << 24);
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} else if (addr == SDIO_CHIP_CLOCK_CSR) {
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if (write == 0) {
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*resp = SBSDIO_ALP_AVAIL | SBSDIO_HT_AVAIL;
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}
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}
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}
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}
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return 0;
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}
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int cyw43_sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t len, uint8_t *buf) {
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printf("cyw43_sdio_transfer_cmd53(write=%d, block_size=%u, arg=%08x, len=%u)\n", write, block_size, arg, len);
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// Decode parameters.
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uint32_t write_decoded = (arg >> 31) & 1;
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uint32_t fn = (arg >> 28) & 0x7;
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uint32_t block_mode = (arg >> 27) & 1;
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uint32_t addr = (arg >> 9) & 0x1ffff;
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uint32_t sz = arg & 0x1ff;
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// Validate parameters.
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assert(write == write_decoded);
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if (block_mode == 0) {
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assert(block_size == sz);
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assert(sz == len);
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} else {
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assert(block_size == 64);
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assert(sz * 64 == len);
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}
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// Ignore SBSDIO_SB_ACCESS_2_4B_FLAG.
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addr &= 0x7fff;
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if (fn == BACKPLANE_FUNCTION) {
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addr += sdio_backplane_cur_addr;
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if (addr < CHIPCOMMON_BASE_ADDRESS) {
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// Read/write backplane memory.
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assert(addr + len <= BACKPLANE_BASE_ADDRESS + BACKPLANE_RAM_SIZE);
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if (write) {
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memcpy(&backplane_ram[addr], buf, len);
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} else {
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memcpy(buf, &backplane_ram[addr], len);
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}
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}
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}
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return 0;
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}
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