This commit is contained in:
Quentin Carbonneaux 2026-04-28 16:48:43 +02:00
parent b8b95a99df
commit 6abea36b9b

View File

@ -380,7 +380,7 @@ Next:
off = e->fn->con[ref.val];
emitcon(&off, e);
if (off.type == CAddr)
if (off.sym.type != SThr || T.apple)
if (off.sym.type != SThr)
fprintf(e->f, "(%%rip)");
break;
case RTmp:
@ -537,6 +537,13 @@ emitins(Ins i, E *e)
assert(isreg(i.to));
con = &e->fn->con[i.arg[0].val];
sym = str(con->sym.id);
if (T.apple && (con->sym.type & SThr)) {
fprintf(e->f,
"\tmovq %s%s@TLVP(%%rip), %%%s\n",
sym[0] == '"' ? "" : T.assym, sym,
regtoa(i.to.val, SLong));
break;
}
if (!T.apple && con->sym.type == SThr) {
/* derive the symbol address from the TCB
* address at offset 0 of %fs */
@ -551,13 +558,6 @@ emitins(Ins i, E *e)
regtoa(i.to.val, SLong));
break;
}
if (T.apple && (con->sym.type & SThr)) {
fprintf(e->f,
"\tmovq %s%s@TLVP(%%rip), %%%s\n",
sym[0] == '"' ? "" : T.assym, sym,
regtoa(i.to.val, SLong));
break;
}
if (!T.apple && con->sym.type == SExtThr) {
/* initial-exec TLS: load offset from
* GOT, add to thread-base register */