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nits
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parent
b8b95a99df
commit
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16
amd64/emit.c
16
amd64/emit.c
@ -380,7 +380,7 @@ Next:
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off = e->fn->con[ref.val];
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off = e->fn->con[ref.val];
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emitcon(&off, e);
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emitcon(&off, e);
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if (off.type == CAddr)
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if (off.type == CAddr)
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if (off.sym.type != SThr || T.apple)
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if (off.sym.type != SThr)
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fprintf(e->f, "(%%rip)");
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fprintf(e->f, "(%%rip)");
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break;
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break;
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case RTmp:
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case RTmp:
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@ -537,6 +537,13 @@ emitins(Ins i, E *e)
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assert(isreg(i.to));
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assert(isreg(i.to));
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con = &e->fn->con[i.arg[0].val];
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con = &e->fn->con[i.arg[0].val];
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sym = str(con->sym.id);
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sym = str(con->sym.id);
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if (T.apple && (con->sym.type & SThr)) {
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fprintf(e->f,
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"\tmovq %s%s@TLVP(%%rip), %%%s\n",
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sym[0] == '"' ? "" : T.assym, sym,
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regtoa(i.to.val, SLong));
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break;
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}
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if (!T.apple && con->sym.type == SThr) {
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if (!T.apple && con->sym.type == SThr) {
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/* derive the symbol address from the TCB
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/* derive the symbol address from the TCB
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* address at offset 0 of %fs */
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* address at offset 0 of %fs */
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@ -551,13 +558,6 @@ emitins(Ins i, E *e)
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regtoa(i.to.val, SLong));
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regtoa(i.to.val, SLong));
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break;
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break;
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}
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}
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if (T.apple && (con->sym.type & SThr)) {
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fprintf(e->f,
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"\tmovq %s%s@TLVP(%%rip), %%%s\n",
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sym[0] == '"' ? "" : T.assym, sym,
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regtoa(i.to.val, SLong));
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break;
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}
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if (!T.apple && con->sym.type == SExtThr) {
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if (!T.apple && con->sym.type == SExtThr) {
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/* initial-exec TLS: load offset from
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/* initial-exec TLS: load offset from
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* GOT, add to thread-base register */
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* GOT, add to thread-base register */
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