disable Singeli bitwiden on SSE2
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@ -167,6 +167,7 @@ def el_s{V=[_]T} = re_el{w_h{T}, V}
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# vector definitions
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def arch_defvw = if (hasarch{'AVX2'}) 256 else 128
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def has_simd = hasarch{'X86_64'} or hasarch{'AARCH64'}
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def has_sel = hasarch{'AVX2'} or hasarch{'AARCH64'}
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def fast_BMI2{} = hasarch{'BMI2'} and not SLOW_PDEP
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# test if vector has a specific width & element type
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@ -23,19 +23,21 @@ def table{w} = each{bitsel_i{w, .}, tup{u8, u16, u32, u64}}
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exportT{'simd_bitsel', table{arch_defvw}}
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fn bitwiden_n_8(src:*void, dst:*void, csz:ux, cam:ux) : void = {
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assert{cam>0}
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assert{(csz>1) & (csz<8)}
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def bulk = arch_defvw / 8
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def V = [bulk]u8
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bitalign{tup{2,8,csz}, 8, {s, align} => {
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@maskedLoop{bulk}(dst in tup{V,*u8~~dst} over cam) {
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dst = align{load{*V~~src}}
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ptr_add{u8, src, bulk*s/8}
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}
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}}
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}
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export{'si_bitwiden_n_8', bitwiden_n_8}
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(if (has_sel) {
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fn bitwiden_n_8(src:*void, dst:*void, csz:ux, cam:ux) : void = {
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assert{cam>0}
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assert{(csz>1) & (csz<8)}
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def bulk = arch_defvw / 8
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def V = [bulk]u8
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bitalign{tup{2,8,csz}, 8, {s, align} => {
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@maskedLoop{bulk}(dst in tup{V,*u8~~dst} over cam) {
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dst = align{load{*V~~src}}
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ptr_add{u8, src, bulk*s/8}
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}
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}}
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}
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export{'si_bitwiden_n_8', bitwiden_n_8}
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})
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(if (hasarch{'AARCH64'}) {
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fn bitnarrow_8_n(src:*void, dst:*void, csz:ux, cam:ux) : void = {
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@ -3,8 +3,6 @@ def __shr{(u16)}{a:T, b} = T~~(re_el{u16,a}>>b)
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def broadcast{[(n*2)]E, x:[n]E} = pair{x, x}
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def pow2_up{v, least} = max{least, 1<<ceil_log2{v}} # least ⌈ ⌈⌾(2⊸⋆⁼) v
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def has_sel = hasarch{'AVX2'} or hasarch{'AARCH64'}
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# make a LUT of at least nt elements in tab, to be indexed by [ni_real≥ni]u8
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# E must be unsigned
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# mode is a hint on expected usage:
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@ -138,7 +138,7 @@ static NOINLINE B zeroPadToCellBits0(B x, usz lr, usz cam, usz pcsz, usz ncsz) {
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// TODO widen 8/16-bit cells to 16/32 via cpyC(16|32)Arr
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if (ncsz<=64 && (ncsz&(ncsz-1)) == 0) {
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u64 tmsk = (1ull<<pcsz)-1;
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#if SINGELI_SIMD
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#if SINGELI_AARCH64 || SINGELI_AVX2
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if (ncsz==8) {
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si_bitwiden_n_8(xp, rp, pcsz, cam);
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goto decG_ret;
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